The 2-way thrashing-avoidance cache (TAC): an efficient instruction cache scheme for object-oriented languages

Chu, Yul; Ito, M.R.

doi:10.1109/iccd.2000.878273

Cited by 4 publications

(5 citation statements)

References 7 publications

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“…Chu and Ito [20] proposed a new instruction cache scheme, named ThrashingAvoidance Cache (TAC). A 2-way TAC scheme employs 2-way banks and XOR mapping functions.…”

Section: Related Workmentioning

confidence: 99%

YAARC: yet another approach to further reducing the rate of conflict misses

Sharifi

Zolfaghari

2007

J Supercomput

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Traditional set associative caches are seriously prone to conflict misses. We propose an adapted new skewed associative architecture as an attempt to alleviate this problem. It has already been shown that skewed associative caches can reduce the rate of conflict misses by using different hash functions to index different banks. Building on this observation, we propose yet another approach to further reduce the rate of conflict misses, nicknamed YAARC (Yet Another Approach to Reducing Conflicts) that uses different hash functions to index into a single bank. Mathematical modeling and simulation results are exploited to evaluate the impact of YAARC on the rate of conflict misses. Mathematical analysis show the superiority of YAARC caches over set and skewed associative caches from the conflict miss point of view. Simulations, using some benchmarks from SPEC CPU2000 benchmark suit that former researchers have reported them as the best candidates for cache performance evaluation, also show nearly 43% conflict miss rate improvement for the skewed associative cache over the set associative cache, and nearly 31% improvement for the YAARC cache over the skewed associative cache. This implies that YAARC caches considerably outperform set and skewed associative caches from the conflict miss point of view. Since production of YAARC caches require a dispensable amount of hardware overhead, they can be considered as a cost effective approach to minimize the rate of conflict misses.

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“…Chu and Ito [20] proposed a new instruction cache scheme, named ThrashingAvoidance Cache (TAC). A 2-way TAC scheme employs 2-way banks and XOR mapping functions.…”

Section: Related Workmentioning

confidence: 99%

YAARC: yet another approach to further reducing the rate of conflict misses

Sharifi

Zolfaghari

2007

J Supercomput

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“…'GoStay2' implies GoStay predict and update rules, as well as a 2-bit flag in the first stage. The first bit of the flag is for the replacement policy of the first stage predictor [5], and the second bit is for the GoStay predict and update rule.…”

Section: Gostaybranch Predictormentioning

confidence: 99%

Section: The 2-way Tac Scheme For the First Stage -The First Mechanismmentioning

confidence: 99%

“…For the first mechanism, we use a 2-way TAC (Thrashing-Avoidance Cache) developed by Chu and Ito [5] for the first stage to reduce conflict misses. The 2-way TAC scheme employs 2 banks and XOR indexing function [5] [6]. Figure 3 shows the main function of the 2-way TAC, which is to place a group of instructions into a bank according to the BSL (Bank Selection Logic) and the BoPLRU (Bank originated Pseudo LRU) replacement policy.…”

Section: The 2-way Tac Scheme For the First Stage -The First Mechanismmentioning

confidence: 99%

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An Efficient Indirect Branch Predictor

Chu

Ito

2001

Euro-Par 2001 Parallel Processing

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In this paper, we present a new hybrid branch predictor called the GoStay2, which can effectively reduce indirect misprediction rates. The GoStay2 has two different mechanisms compared to other 2-stage hybrid predictors that use a Branch Target Buffer (BTB) as the first stage predictor: Firstly, to reduce conflict misses in the first stage, a new effective 2-way cache scheme is used instead of a 4-way set-associative. Secondly, to reduce mispredictions caused by an inefficient predict and update rule, a new selection mechanism and update rule are proposed. We have developed a simulation program by using Shade and Spixtools, provided by SUN Microsystems, on an Ultra SPARC/10 processor. Our results show that the GoStay2 improves indirect misprediction rates of a 64-entry to 4K-entry BTB (with a 512-or 1Kentry PHT) by 14.9% to 21.53% compared to the leaky filter.

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“…There are also some hardware solutions for thrashing which are implemented in the cache [10,11]. Usually LRU is the basic scheme behind both hardware and software victim selection algorithms.…”

Section: Introductionmentioning

confidence: 99%

Medium-Term Scheduler as a Solution for the Thrashing Effect

Reuven

Wiseman

2005

The Computer Journal

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We suggest a method for minimizing the paging on a system with a very heavy memory usage. Sometimes there are processes with active memory allocations that should be in the physical memory, but their total size exceeds the physical memory range. In such cases, the operating system starts swapping pages in and out of the memory on every context switch. We minimize this thrashing by splitting the processes into a number of bins, using Bin Packing approximation algorithms. We modify the scheduler to have two levels of scheduling-medium-term scheduling and short-term scheduling. The medium-term scheduler switches the bins in a Round-Robin manner, whereas the short-term scheduler runs the standard Linux scheduler among the processes in each bin. We show that this feature does not impose modifications on the shared memory maintenance. In addition, we show how to adjust the new scheduler to fit some elements of the original scheduler like priority and real-time privileges. Experimental results show significant improvement on heavily loaded memories. The code of this project is free and can be found in http://www.cs.biu.ac.il/~reubenm.

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The 2-way thrashing-avoidance cache (TAC): an efficient instruction cache scheme for object-oriented languages

Cited by 4 publications

References 7 publications

YAARC: yet another approach to further reducing the rate of conflict misses

YAARC: yet another approach to further reducing the rate of conflict misses

An Efficient Indirect Branch Predictor

Medium-Term Scheduler as a Solution for the Thrashing Effect

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