&lt;italic&gt;pd-gem5&lt;/italic&gt;: Simulation Infrastructure for Parallel/Distributed Computer Systems

Alian, Mohammad; Kim, Daehoon; Kim, Nam Sung

doi:10.1109/lca.2015.2438295

Cited by 25 publications

(9 citation statements)

References 5 publications

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“…A Linux (MPSoC Zynq-7000-ARM Cortex-A9 dual-core) has been used, such as in [14], to test virtual and physical interactions and using different setups. To test virtual interaction, it will run the Linux boot and the ParMiBench benchmark, which is specialized in multi-core embedded devices.…”

Section: Test and Resultsmentioning

confidence: 99%

“…The most common approach to build a virtual platform consists of an open-source processor emulator to reproduce the behavior of the software execution, such as QEMU [13] or Gem5 [14]; and a hardware simulator such as SystemC, which enables modeling the hardware designs from the algorithm level to the Register-Transfer Level (RTL).…”

Section: Background and Proposal Description 21 Hardware/software Cmentioning

confidence: 99%

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Enabling Parallelized-QEMU for Hardware/Software Co-Simulation Virtual Platforms

et al. 2021

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Presently, the trend is to increase the number of cores per chip. This growth is appreciated in Multi-Processor System-On-Chips (MPSoC), composed of more cores in heterogeneous and homogeneous architectures in recent years. Thus, the difficulty of verification of this type of system has been great. The hardware/software co-simulation Virtual Platforms (VP) are presented as a perfect solution to address this complexity, allowing verification by simulation/emulation of software and hardware in the same environment. Some works parallelized the software emulator to reduce the verification times. An example of this parallelization is the QEMU (Quick EMUlator) tool. However, there is no solution to synchronize QEMU with the hardware simulator in this new parallel mode. This work analyzes the current software emulators and presents a new method to allow an external synchronization of QEMU in its parallelized mode. Timing details of the cores are taken into account. In addition, performance analysis of the software emulator with the new synchronization mechanism is presented, using: (1) a boot Linux for MPSoC Zynq−7000 (dual-core ARM Cortex-A9) (Xilinx, San Jose, CA, USA); (2) an FPGA-Linux co-simulation of a power grid monitoring system that is subsequently implemented in an industrial application. The results show that the novel synchronization mechanism does not add any appreciable computational load and enables parallelized-QEMU in hardware/software co-simulation virtual platforms.

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Section: Test and Resultsmentioning

confidence: 99%

Section: Background and Proposal Description 21 Hardware/software Cmentioning

confidence: 99%

Enabling Parallelized-QEMU for Hardware/Software Co-Simulation Virtual Platforms

et al. 2021

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“…This work adopts the state-of-the-art gem5 simulator [4] for three main reasons: (1) the gem5 source code is open and several extensions have been proposed in the past [1,18], (2) the gem5 enables microarchitectural cycle-accurate simulation in an acceptable time (i.e., 0.4-2 MIPS depending on the application workload), and (3) it supports the current ARM Cortex-A architectures. Moreover, we use the processor model for the ARM Cortex-A9 (ARMv7) and Cortex-A72 (ARMv8) with single, dual, and quad-core variants.…”

Section: Simulatormentioning

confidence: 99%

“…The new 64-bit ISA also enlarges the integer register-file, from 16 to 32 registers, increasing the number of possible targets for fault injection by a factor of four. However, the compiler algorithm uses a reduced fraction of the available registers for load/store and control flow operations leaving other registers 1 The number of radiant-energy particles incident on the target system surface in a given period of time for global variables or unused. As in this experiment each register suffers an identical number of fault injections, critical registers (e.g., program counter, stack pointer, those used on load/store and control flow operations) are less likely to face faults in the ARMv8 rather than in the ARMv7.…”

Section: Register Filementioning

confidence: 99%

Extensive Evaluation of Programming Models and ISAs Impact on Multicore So Error Reliability

Rosa¹,

Bandeira²,

Reis³

et al. 2018

2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

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“…The first family focuses on the increasing of computational power, e.g., increasing the number of simulated events per second. Usually it is achieved by running the simulation distributed across multiple host machines [6], [7]. Distributed simulation is a known difficult technique as one must carefully deal with simulation partitioning and event synchronizations among available hosts.…”

Section: A Traditional Simulatorsmentioning

confidence: 99%

ElasticSimMATE: A fast and accurate gem5 trace-driven simulator for multicore systems

Nocua

Bruguier

Sassatelli

et al. 2017

2017 12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)

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Multicore system analysis requires efficient solutions for architectural parameter and scalability exploration. Long simulation time is the main drawback of current simulation approaches. In order to reduce the simulation time while keeping the accuracy levels, trace-driven simulation approaches have been developed. However, existing approaches do not allow multicore exploration or do not capture the behavior of multithreaded programs. Based on the gem5 simulator, we developed a novel synchronization mechanism for multicore analysis based on the trace collection of synchronization events, instruction and dependencies. It allows efficient architectural parameter and scalability exploration with acceptable simulation speed and accuracy.

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<italic>pd-gem5</italic>: Simulation Infrastructure for Parallel/Distributed Computer Systems

Cited by 25 publications

References 5 publications

Enabling Parallelized-QEMU for Hardware/Software Co-Simulation Virtual Platforms

Enabling Parallelized-QEMU for Hardware/Software Co-Simulation Virtual Platforms

Extensive Evaluation of Programming Models and ISAs Impact on Multicore So Error Reliability

ElasticSimMATE: A fast and accurate gem5 trace-driven simulator for multicore systems

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