The manufacture of modern semiconductor devices widely uses tungsten contacts on silicon to achieve highly reliable circuits with sub-0.5 m design rules. Normally the process flow consists of an integrated physically vapor deposited (PVD) Ti/TiN diffusion barrier and wetting layer followed by a thermal annealing step prior to the tungsten deposition. The anneal step in N 2 /H 2 atmosphere improves contact resistance by forming TiSi x at the bottom of the contact hole. In addition the barrier properties of the Ti/TiN films improve later, preventing the attack of titanium or silicon by fluorine during the W chemical vapor deposition (CVD) deposition process normally causing poor contact resistance due to "volcano" or high leakage currents due to "worm hole" defects. 1,2 The aggressive trends in shrinking of semiconductor device structures are leading to a continuous increase in aspect ratio (depth/diameter) of contacts and vias. On this shrink roadmap it is expected that PVD TiN films will reach their limits mainly due to poor bottom and sidewall coverage. In the semiconductor industry it has been proposed to overcome these problems by using CVD-TiN. To minimize the effort of implementing CVD-TiN in production it is of great interest to run the CVD-TiN process in a seperated system nonintegrated with the PVD Ti deposition. Consequently, this approach requires an air break between the deposition of PVD-Ti and CVD-TiN films with a native titanium oxide film on top of the Ti layer. Our experimental work shows that the oxide causes higher contact resistance independent of the CVD-TiN used but influenced by the achieved bottom thickness of the Ti layer in the contact hole. The influence of the higher oxygen content caused by the air break in the PVD-Ti/CVDTiN film and the diffusion of oxygen into connecting films on the contact resistance is studied based on electrical results with TEM, Auger analysis, and electron energy loss (EEL) spectroscopy of device geometries.
ExperimentalDetailed investigations were performed on PVD-Ti/CVD-TiN layer structures deposited on Si substrates either as blanked films or in fully integrated wafers of a 16M dynamic random access memory (DRAM) technology.The Ti deposition was done on an Electrotech Sigma 200 PVD sputter system with a long throw sputter module with increased target-to-substrate distance of 245 mm. 3 Sputtering was achieved in argon atmosphere with a pressure around several millitorrs. During deposition the wafer temperature reached a value between 200 and 300ЊC. The wafer was actively cooled down prior to air exposure.For the CVD-TiN process the different suggested metallorganic precursors in semiconductor technology are titanium chloride (TiCl 4 ), 4 tetrakis(dimethylamino) titanium (TDMAT), 5 and tetrakis-(diethylamino) titanium (TDEAT). 6 The use of TDMAT or TDEAT offers the advantages of low temperature deposition and low risks of chlorine contamination. For these experiments, the CVD-TiN was deposited in a single chamber, multistation reactor of a Novellus concept 2 p...