&lt;title&gt;Free-space optical interconnect system using polarization-rotating modulator arrays&lt;/title&gt;

McCarthy, Aongus; Tooley, F. A. P.; Laprise, Emmanuelle; Plant, David V.; Kirk, Andrew G.; Oren, M.; Lu, Yicheng

doi:10.1117/12.386842

Cited by 2 publications

(1 citation statement)

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“…Several arrays of photodetectors and emitters (ranging from 8x8 to 32x32) have been demonstrated by different groups with a device pitch as small as 125 microns [14,15,16,17] showing that integrating a density of about 5000 optical IO/cm 2 on top of CMOS chips is feasible.…”

Section: A Optical Interconnects For a Symmetric Multiprocessor Cachmentioning

confidence: 99%

Parallel optical interconnects may reduce the communication bottleneck in symmetric multiprocessors

Collet¹,

Hlayhel²,

Litaize³

2001

Appl. Opt.

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We start with a detailed analysis of the communication issues in today's symmetric multiprocessor (SMP) architectures to study the benefits of implementing optical interconnects (OI) in these machines. We show that the transmission of block addresses is the most critical communication bottleneck of future large SMPs owing to the need to preserve the coherence of data duplicated in caches. An address transmission bandwidth as high as 200-300 Gb/s may be necessary in ten years from now; this requirement will represent a difficult challenge for shared electric buses. In this context we suggest the introduction of simple point-to-point OIs for a SMP cache-coherent switch, i.e., for a VLSI switch that would emulate the shared-bus function. The operation might require as much as 10,000 input-outputs (IOs) to connect 100 processors, particularly if one maintains the present parallelism of transmissions to preserve a large bandwidth and a short memory access latency. The interest for OIs comes from the potential increase of the transmission frequency and from the possible integration of such a high density of IOs on top of electronic chips to overcome packaging issues. Then we consider the implementation of an optical bus that is a multipoint optical line involving more optical technology. This solution allows multiple simultaneous accesses to the bus, but the preservation of the coherence of caches can no longer be maintained with the usual fast snooping protocols.

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Section: A Optical Interconnects For a Symmetric Multiprocessor Cachmentioning

confidence: 99%