<title>Implications of triple patterning for 14nm node design and patterning</title>

Abstract

The upcoming 14nm logic node will require lithographic patterning of complex layout patterns with minimum pitches of approximately 44nm to 50nm. This requirement is technically feasible by reusing existing 20nm litho-etch-litho-etch (LELE) double patterning (DPT) methods with very strong restricted design rules. However, early indications are that the cost-effective design and patterning of these layouts will require lithographic methods with additional resolution, especially in two-dimensional configurations. If EUV lithography reaches maturity too late, the 14nm logic node will need other lithographic techniques and the corresponding physical design rules and EDA methodologies to be available. Triple patterning technology (TPT) is a strong option for 14nm node logic on both hole and line-space pattern layers. In this paper we study major implications of a 14nm logic TPT lithographic solution upon physical design, design rules, mask synthesis/EDA algorithms and their process interactions.

Layout Decomposition for Triple Patterning Lithography

“…Triple patterning lithography, which is a natural extension from double patterning lithography, is one of most viable solutions for 14 nm node [4]. In addition, industry has already explored the test-chip patterns with triple patterning or even quadruple patterning [5].…”

Comprehensive Performance Analysis of Interconnect Variation by Double and Triple Patterning Lithography Processes

“…The TPL process, however, will be widely used for the 14-nm technology node and beyond [1,6,11]. Thus we conduct TPL statistical variation simulations based on the geometry of the 14-nm technology node [1].…”

“…Recently, the triple patterning lithography (TPL), or litho-etch-litho-etch-litho-etch (LELELE), has been proposed for backend patterning of a 14-nm node in which the minimum metal pitch can be below 50 nm [1,5,6,11,12]. In TPL, three individual layers or masks can be generated in a layout decomposition as a direct extension of DPT.…”

Toward Unidirectional Routing Closure in Advanced Technology Nodes

“…In general, there exist two types of MPL, Litho-Etch-Litho-Etch (LELE) type and self-aligned type. LELE-type of MPL allows stitch insertions and two-dimensional patterns [27], [59], [70], [71], [77], but coloring and overlay compensation schemes become extremely complicated for triple patterning lithography and beyond [12], [15], [30], [38], [60], [73], [76], [81]. Self-aligned type of MPL can minimize electrical variations from overlay and line-edge-roughness but introduces complex coloring and line-end constraints [40], [42], [56].…”