Double patterning has gained prominence as the most likely methodology to help keep Moore's law going towards 22nm ½ pitch lithography. However, most designs cannot be blindly shrunk to run using only two patterning layers and a variety of constraints must be imposed on designs to allow for correct decomposition. These constraints are more onerous for the contact layer than for line/space patterns because they more easily form odd cycles on the 2D plane, which cannot be broken using polygon cutting. As this can adversely limit packing density, especially in bit cells, a triple patterning decomposition capability could be attractive for the contact layer. Pattern decomposition for contacts can be likened to coloring a map where minimum spaces between contacts are replaced with borders. It is well known that 4 colors can color any map [5,6], but it is an NP-complete problem to compute the minimum number of colors needed to color any given map [7]. This should place an upper limit on the scalability of any algorithm able to color large networks. A variety of test patterns that are known 3-colorable are needed to compare suitable algorithms. It has been proved that a set of aperiodic tiling known as "Penrose Tiles" is 3-colorable [8]. This paper compares the scalability of different coloring algorithms using a variety of contact patterns based on Penrose Tiles.

The upcoming 14nm logic node will require lithographic patterning of complex layout patterns with minimum pitches of approximately 44nm to 50nm. This requirement is technically feasible by reusing existing 20nm litho-etch-litho-etch (LELE) double patterning (DPT) methods with very strong restricted design rules. However, early indications are that the cost-effective design and patterning of these layouts will require lithographic methods with additional resolution, especially in two-dimensional configurations. If EUV lithography reaches maturity too late, the 14nm logic node will need other lithographic techniques and the corresponding physical design rules and EDA methodologies to be available. Triple patterning technology (TPT) is a strong option for 14nm node logic on both hole and line-space pattern layers. In this paper we study major implications of a 14nm logic TPT lithographic solution upon physical design, design rules, mask synthesis/EDA algorithms and their process interactions.

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IC layouts are typically defined with simple shapes such as rectangles and 45° triangles. Fundamental limitations in the imaging process unavoidably prevent the exact rendering of these shapes on the wafer, and this necessitates an interpretation of what should appear on silicon. For example, an OPC tool must interpret a square corner as something more rounded, otherwise the pursuit of the ideal shape may lead to bridging and/or Mask Rule Check (MRC) violations. A solution to this is to move the target points for Optical Proximity Correction (OPC) off from the GDS edges and onto mathematically described curves inscribed within the corners of the design polygon and use these as the target for OPC correction. Suitable values for the radius of these curves depend on the model used, the geometry they are applied to, and the requirements of the device the shape builds. An uncorrected square corner gives a printed contour whose radius of curvature, nearest the design corner, provides a target radius for a low impact OPC correction. Line ends, right angled bends in tracks and end caps all need separate optimization in terms of the best radius of target curve to use. By understanding whether the design priority is for CD control (such as poly gate) or for positional accuracy (such as contact enclosure) the OPC correction parameters and final target shape can be modified in such a way to best realize these interpreted goals.