&lt;title&gt;Integrated applications of inspection data in the semiconductor manufacturing environment&lt;/title&gt;

Tobin, Kenneth W.; Karnowski, Thomas P.; Lakhani, Fred

doi:10.1117/12.429361

Cited by 28 publications

(7 citation statements)

References 18 publications

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“…Three major affected elements are the used Slurry, the Wafer, and the Polishing Pad of a CMP machine in the reaction focus as shown in figure 1. [7] Fig. 1 A typical rotary grinding CMP machine [7] The purpose of cleaning a wafer is not damaged or degraded under the premise of the wafer surface.…”

Section: Introductionmentioning

confidence: 99%

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Multi-Objective Optimization of Cleaning Process for LAO Wafers Using Grey Relational Analysis

Yang

Huang

Tsai

2012

AMR

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The light emitting diode (LED) development technology is an important topic for green industry. This study focused on the efficient cleaning for LAO hydrolysis material, which is a potential LED substrate. The 99.5% ethanol or an alternative solution is used to clean the LAO substrate and dry with the help of anhydrous gas. To improve the cleaning performance, the Taguchi-based orthogonal array of experimental planning and the Grey Relation Analysis are employed to optimize the cleaning parameters. Four control factors are cleaning time, soaking time, PVA sponge type, drying method. The multiple performance characteristics of responses include the residual traces of impurities and water mark after the cleaning process for LAO substrate. With the proposed cleaning process, the surface foreign matter removal rate of target 80% and the residual water marks of declining to 20% are achieved.

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Section: Introductionmentioning

confidence: 99%

“…[7] Fig. 1 A typical rotary grinding CMP machine [7] The purpose of cleaning a wafer is not damaged or degraded under the premise of the wafer surface. The wafer surface is attached to remove dusts and impurities.…”

Section: Introductionmentioning

confidence: 99%

Multi-Objective Optimization of Cleaning Process for LAO Wafers Using Grey Relational Analysis

Yang

Huang

Tsai

2012

AMR

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“…The main purposes of the wafer defect inspection were finding out defective dies and discard them. In general, the inspection methods can be roughly categorized into two types: electric inspection and post-sawing inspection [1][2][3][4][5][6]. Electric inspection need additional wafer space for testing circuits results in the unit cost increasing.…”

Section: Introductionmentioning

confidence: 99%

“…In addition, the process can incur significant personnel costs. There have been several methods developed for wafer inspection [1][2][3][4][5][6]. Tobin et al [4] integrated image process techniques and database system for wafer defect inspection.…”

Section: Introductionmentioning

confidence: 99%

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A Hierarchical Self-Organizing Neural Network for Automatic Wafer Defect Inspection

Chang

2006

MSF

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The wafer defect inspection is an important process before die packaging. The defective regions were usually identified through visual judgment with the aid of a scanning electron microscope. Dozens of people visually check dies and mark their regions manually. Thus, potential misjudgment may be introduced due to human fatigue. In addition, the process can incur significant personnel costs. Self-Organizing Neural Networks (SONNs) have been proven to have the capabilities of unsupervised auto-clustering. In this paper, a hierarchical self-organizing neural networks (HSONN) with consideration of multiple textural information is proposed to replace the traditional electrical testing and the human inspection processes. The proposed HSONN is consists of 3 layers, each layer is a specific cluster to separate the block of wafer image into normal and defective regions. The suspicious defective regions are used as inputs to the next layer of HSONN for subsequent classification of the defective regions. Through the hierarchical classify, the output of the 3th layer denotes the detecting defective regions. Based on real-world data, the experimental results show that the proposed method successfully identifies the defective regions on wafers with good performances.

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Simulation Studies of Two-Layer Hopfield Neural Networks for Automatic Wafer Defect Inspection

Chang

Wang

Lin

2006

Advances in Applied Artificial Intelligence

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<title>Integrated applications of inspection data in the semiconductor manufacturing environment</title>

Cited by 28 publications

References 18 publications

Multi-Objective Optimization of Cleaning Process for LAO Wafers Using Grey Relational Analysis

Multi-Objective Optimization of Cleaning Process for LAO Wafers Using Grey Relational Analysis

A Hierarchical Self-Organizing Neural Network for Automatic Wafer Defect Inspection

Simulation Studies of Two-Layer Hopfield Neural Networks for Automatic Wafer Defect Inspection

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