&lt;title&gt;Investigation of the physical and practical limits of dense-only phase-shift lithography for circuit feature definition&lt;/title&gt;

Tyrrell, Brian; Fritze, M.; Mallen, Renee D.; Wheeler, Bruce; Rhyins, Peter D.; Martin, Patrick

doi:10.1117/12.475686

Cited by 5 publications

(5 citation statements)

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“…To include other features on the layer such as the horizontally-oriented poly-silicon connection paths and contact-landing pads, whose dimensions are not critical for cell area and can be designed larger, many * A transistor pitch, also called a "contacted pitch", is the minimum pitch between two gates with a contact between them. other template-trim approaches can be used 12,14,15,18 and the final number of exposures, masks, and resistor layers might be different. For example, since most of the gate are vertically-orientated in standard cells, it is a suitable application of Canon IDEAL method.…”

Section: Lithographic Methods For Gridded Layout Standard Cellsmentioning

confidence: 99%

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Performance optimization for gridded-layout standard cells

Wang

Wong²,

Lam

2004

SPIE Proceedings

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The grid placement of contacts and gates enables more effective use of resolution enhancement techniques, which in turn allow a reduction of critical dimensions. Although the regular placement adds restrictions during cell layout, the overall circuit area can be made smaller and the extra manufacturing cost can be kept to the lowest by a careful selection of the grid pitch, using template-trim lithography method, allowing random contact placement in the vertical direction, and using rectangular rather than square contacts. The purpose of this work is to optimize the gridded-layout-based process. The trade-off between the layout area and manufacturing cost, and the determination of the minimum grid pitch are discussed in this paper. We demonstrate that it is a 1-D scaling instead of the conventional 2-D scaling for standard cells and the narrow MOSFETs inside after the application of the gridded layout on the contact and gate levels. The corresponding effects on circuit performances, including the leakage current, are also explored.

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Section: Lithographic Methods For Gridded Layout Standard Cellsmentioning

confidence: 99%

“…Because there are many template-trim approaches available 12,14,15,18 for the poly-silicon layer, the final number of exposures, masks, and resistor layers might be different, leading to different impact on design rules and manufacturing cost.…”

Section: Layout Area Vs Manufacturing Costmentioning

confidence: 99%

Performance optimization for gridded-layout standard cells

Wang

Wong²,

Lam

2004

SPIE Proceedings

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“…In passing, we comment that in fact, the idea of putting the entire pattern on a regular grid is not new, and was considered previously in the literature [7,9,11,13,14,15], although it really reached center stage with the design concept Intel implemented in its 45nm processors [8].…”

Section: D Gridded Design Rules (Gdr)mentioning

confidence: 99%

Improved mask-based CD uniformity for gridded-design-rule lithography

Faivishevsky

Khristo

Sagiv

et al. 2009

Metrology, Inspection, and Process Control for Microlithography XXIII

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The difficulties encountered during lithography of state-of-the-art 2D patterns are formidable, and originate from the fact that deep sub-wavelength features are being printed. This results in a practical limit of 4 . 0 1 ≥ k as well as a multitude of complex restrictive design rules, in order to mitigate or minimize lithographic hot spots. An alternative approach, that is gradually attracting the lithographic community's attention, restricts the design of critical layers to straight, dense lines (a 1D grid), that can be relatively easily printed using current lithographic technology. This is then followed by subsequent, less critical trimming stages to obtain circuit functionality. Thus, the 1D gridded approach allows hotspot-free, proximity-effect free lithography of ultra low-1 k features. These advantages must be supported by a stable CD control mechanism. One of the overriding parameters impacting CDU performance is photo mask quality. Previous publications have demonstrated that IntenCD™ -a novel, mask-based CDU mapping technology running on Applied Materials' Aera2™ aerial imaging mask inspection tool -is ideally fit for detecting mask-based CDU issues in 1D (L&S) patterned masks for memory production. Owing to the aerial nature of image formation, IntenCD directly probes the CD as it is printed on the wafer. In this paper we suggest that IntenCD is naturally fit for detecting mask-based CDU issues in 1D GDR masks. We then study a novel method of recovering and quantifying the physical source of printed CDU, using a novel implementation of the IntenCD technology. We demonstrate that additional, simple measurements, which can be readily performed on board the Aera2™ platform with minimal throughput penalty, may complement IntenCD and allow a robust estimation of the specific nature and strength of mask error source, such as pattern width variation or phase variation, which leads to CDU issues on the printed wafer. We finally discuss the roles played by IntenCD in advanced GDR mask production, starting with tight control over mask production process, continuing to mask qualification at mask shop and ending at in-line wafer CDU correction in fabs.

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“…The double-exposure lithographic approach in the example forms only vertically oriented fine features on a polysilicon layer. To include other features on the layer such as the horizontally oriented polysilicon connection paths and contact-landing pads, whose dimensions are not critical for cell area and can be designed larger, many other template-trim approaches can be used, 12,13,16,18,23 and the final number of exposures and masks might be different. For example, since most of the gates are vertically orientated in standard cells, it is a suitable application of Canon IDEAL method.…”

Section: Lithographic Approachesmentioning

confidence: 99%

“…Based on the OAI or an alternating phase-shifting mask ͑alt-PSM͒, many advanced lithographic approaches have been proposed recently for contacts and gates that employ regular layout placement, pushing the k 1 to about its minimum value. [11][12][13][14][15][16][17][18] However, on the other hand, from a layout designer point of view, the regular placement imposes extra restriction on layout compaction. Although the gates and contacts can be designed smaller and packed closer, the regular placement may be so restrictive on layout compaction that the final circuit area increases unacceptably.…”

Section: Introductionmentioning

confidence: 99%

Standard cell design with resolution-enhancement-technique-driven regularly placed contacts and gates

Wang

Wong²,

Lam

2005

J. Micro/Nanolith. MEMS MOEMS

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The practicability and methodology of applying resolutionenhancement-technique-driven regularly placed contacts and gates on standard cell layout design are studied. The regular placement enables more effective use of resolution enhancement techniques (RETs), which in turn enables a reduction of critical dimensions. Although regular placement of contacts and gates adds restrictions during cell layout, the overall circuit area can be made smaller and the number of extra masks and exposures can be kept to the lowest by careful selection of the grid pitch, using template-trim chromeless phase-shifting lithography approaches, enabling unrestricted contact placement in one direction, and using rectangular rather than square contacts. Four different fabrication-friendly layouts are compared. The average area change of 64 standard cells in a 130-nm library range from Ϫ4.2 to Ϫ15.8% with the four fabricationfriendly layout approaches. The area change of five test circuits using the four approaches range from Ϫ16.2 to ϩ2.6%. Dynamic power consumption and intrinsic delay also improve with the decrease in circuits area, which is verified with the examination results. © 2005 Society of Photo-Optical Instrumentation Engineers.

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<title>Investigation of the physical and practical limits of dense-only phase-shift lithography for circuit feature definition</title>

Cited by 5 publications

References 0 publications

Performance optimization for gridded-layout standard cells

Performance optimization for gridded-layout standard cells

Improved mask-based CD uniformity for gridded-design-rule lithography

Standard cell design with resolution-enhancement-technique-driven regularly placed contacts and gates

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