&lt;title&gt;MASPINN: novel concepts for a neuroaccelerator for spiking neural networks&lt;/title&gt;

Schoenauer, T.; Mehrtash, N.; Jahnke, Andreas; Klär, H.

doi:10.1117/12.343072

Cited by 15 publications

(8 citation statements)

References 9 publications

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“…In order to achieve real-time computation of very complex SANNs we proposed an accelerator system called memory optimized accelerator for spiking neural networks (MASPINN), which is an accelerator board connected to a host computer via a PCI-bus [13]. As shown in Fig.…”

Section: Accelerator System For Spiking Neural Network: Maspinnmentioning

confidence: 99%

NeuroPipe-Chip: A digital neuro-processor for spiking neural networks

Schoenauer

Atasoy

Mehrtash

et al. 2002

IEEE Trans. Neural Netw.

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Computing complex spiking artificial neural networks (SANNs) on conventional hardware platforms is far from reaching real-time requirements. Therefore we propose a neuro-processor, called NeuroPipe-Chip, as part of an accelerator board. In this paper, we introduce two new concepts on chip-level to speed up the computation of SANNs. These concepts are implemented in a prototype of the NeuroPipe-Chip. We present the hardware structure of the prototype and evaluate its performance in a system simulation based on a hardware description language (HDL). For the computation of a simple SANN for image segmentation, the NeuroPipe-Chip operating at 100 MHz shows an improvement of more than two orders of magnitude compared to an Alpha 500 MHz workstation and approaches real-time requirements for the computation of SANNs in the order of 10(6) neurons. Hence, such an accelerator would allow for applications of complex SANNs to solve real-world tasks like real-time image processing. The NeuroPipe-Chip has been fabricated in an Alcatel 0.35-mum digital CMOS technology.

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Section: Accelerator System For Spiking Neural Network: Maspinnmentioning

confidence: 99%

NeuroPipe-Chip: A digital neuro-processor for spiking neural networks

Schoenauer

Atasoy

Mehrtash

et al. 2002

IEEE Trans. Neural Netw.

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“…Several architectures have already been presented, ranging from large systems [13], [14], [15] able to process very large networks (> 10, 000 of neurons) at many times real-time speed, to compact designs where small networks are directly mapped onto hardware [6], [16], [17], [18] using small neuron processing elements (PEs). These implementations span a small part of a larger design space which allows to make a trade-off between area (chip area and memory footprint) and calculation time.…”

Section: Introductionmentioning

confidence: 99%

Compact hardware for real-time speech recognition using a Liquid State Machine

Schrauwen

D’Haene

Verstraeten

et al. 2007

2007 International Joint Conference on Neural Networks

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Hardware implementations of Spiking Neural Networks are numerous because they are well suited for implementation in digital and analog hardware, and outperform classic neural networks. This work presents an application driven digital hardware exploration where we implement realtime, isolated digit speech recognition using a Liquid State Machine (a recurrent neural network of spiking neurons where only the output layer is trained). First we test two existing hardware architectures, but they appear to be too fast and thus area consuming for this application. Then we present a scalable, serialised architecture that allows a very compact implementation of spiking neural networks that is still fast enough for real-time processing. This work shows that there is actually a large hardware design space of Spiking Neural Network hardware that can be explored. Existing architectures only spanned part of it.

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“…(Schoenauer et al, 1998). The key concepts of an efficient mapping are load balancing over an array of processing elements, minimizing inter processing element communication and minimizing synchronization between the processing elements (PEs).…”

Section: Mapping Neural Network On Parallel Computersmentioning

confidence: 99%