&lt;title&gt;Suspended thermal oxide trench isolation for SCS MEMS&lt;/title&gt;

Webb, Russell Y.; Adams, Scott G.; MacDonald, N.C.

doi:10.1117/12.325740

Cited by 7 publications

(10 citation statements)

References 6 publications

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“…10. There are oxidized trenches that are present on free standing beams to isolate one section of the beam from another (Webb et al, 1998). This kind of a scheme becomes more difficult to implement when the This technique also requires an extra mask level to make the trenches before the Z actuator structures are fabricated.…”

Section: Isolation Requirementsmentioning

confidence: 99%

A single crystal silicon 3 dimensional processing technique with applications in large displacement electrostatic actuation

Subramanian

Huang

MacDonald

2002

Microsystem Technologies

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A new process has been developed to produce mechanical structures of multiple levels on a silicon substrate. The process lends itself to high aspect ratio bulk micromachining of single crystal silicon. Structures can be fabricated at multiple levels with a single lithography step and without alignment requirements. Any required difference in height between levels is defined precisely at intermediate etch steps. One application of this process utilizes the out of plane asymmetries produced by the multiple levels to create a large displacement, large force and highly linear out of plane actuator stage. This technique is easily combined with single level high aspect ratio MEMS processing methods.

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Section: Isolation Requirementsmentioning

confidence: 99%

A single crystal silicon 3 dimensional processing technique with applications in large displacement electrostatic actuation

Subramanian

Huang

MacDonald

2002

Microsystem Technologies

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“…It represents a nanoscale version of the single-crystal reactive etching and metallization (SCREAM) process, [28] where both the NW and MEMS are fabricated within the SOI device layer in a monolithic fashion. Originally developed for the fabrication of free-standing Si micromechanical structures within bulk Si substrates, [29][30][31][32][33][34][35] the technique was recently extended into the nanoscale. [36][37][38][39][40] Using a two-stage etching technique, NWs are obtained at the upper surface of the device layer, i.e., coplanar with the MEMS surface.…”

Section: Fabrication Techniquesmentioning

confidence: 99%

Silicon Nanowires Driving Miniaturization of Microelectromechanical Systems Physical Sensors: A Review

et al. 2023

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The miniaturization of microelectromechanical systems (MEMS) physical sensors is driven by global connectivity needs and is closely linked to emerging digital technologies and the Internet of Things. Strong technical advantages of miniaturization such as improved sensitivity, functionality, and power consumption are accompanied by significant economic benefits due to semiconductor manufacturing. Hence, the trend to produce smaller sensors and their driving force resemble very much those of the miniaturization of integrated circuits (ICs) as described by Moore's law. In this respect, with its IC‐, and MEMS‐compatibility, and scalability, the silicon nanowire is frequently employed in frontier research as the sensor building block replacing conventional sensors. The integration of the silicon nanowire with MEMS has thus generated a multiscale hybrid architecture, where the silicon nanowire serves as the piezoresistive transducer and MEMS provide an interface with external forces, such as inertial or magnetic. This approach has been reported for almost all physical sensor types over the last decade. These sensors are reviewed here with detailed classification. In each case, associated technological challenges and comparisons with conventional counterparts are provided. Future directions and opportunities are highlighted.

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“…Several methods of bulk micromachining [4][5][6][7][8] based on standard silicon wafers are proposed as an alternative to the standard SOI technology. All these methods employ deep reactive ion etching (DRIE) to pattern, a passivation layer to protect and plasma isotropic etching to release structures in the bulk material.…”

Section: Introductionmentioning

confidence: 99%

“…All these methods employ deep reactive ion etching (DRIE) to pattern, a passivation layer to protect and plasma isotropic etching to release structures in the bulk material. Different techniques are used to electrically isolate the released structures from the bulk material: by metallization [4,5], by creating silicon islands surrounded by electrically insulating silicon oxide [6], by the use of aluminium interconnects to fasten released components [7] or by the employment of suspended thermal silicon oxide isolation segments [8].…”

Section: Introductionmentioning

confidence: 99%

“…In addition to electrical isolation from the substrate, the isolation technology employing the suspended thermal oxide segments [8] can provide electrical isolation between mechanically connected structures, exploiting all benefits of the SOI compatible trench isolation technology and avoiding at the same time the drawbacks associated with the use of SOI wafers.…”

Section: Introductionmentioning

confidence: 99%

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Advanced plasma processing combined with trench isolation technology for fabrication and fast prototyping of high aspect ratio MEMS in standard silicon wafers

Sarajlic

Boer

Jansen

et al. 2004

J. Micromech. Microeng.

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A bulk micromachining technology for fabrication of micro electro mechanical systems (MEMS) in a standard silicon wafer is presented. A fabrication process, suitable for full integration with on-chip electronics, employs advanced plasma processing to etch, passivate and release micromechanical structures in a single plasma system, and vertical trench isolation to obtain electrical isolation between the released components. Distinct electrical domains can be defined even on movable parts. The sophisticated electrical isolation between high-aspect-ratio single-crystal silicon (SCS) components allows simplification of the fabrication and improvement of the performance of existing devices and design of entirely new MEMS. The presented technology is an attractive platform for both fabrication and rapid prototyping of MEMS. This is due to a short processing time, a large freedom of design, high process flexibility and low-cost of the starting SCS substrate relative to SOI substrates. Several example microstructures demonstrating the capabilities of this technology have been successfully fabricated.

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<title>Suspended thermal oxide trench isolation for SCS MEMS</title>

Cited by 7 publications

References 6 publications

A single crystal silicon 3 dimensional processing technique with applications in large displacement electrostatic actuation

A single crystal silicon 3 dimensional processing technique with applications in large displacement electrostatic actuation

Silicon Nanowires Driving Miniaturization of Microelectromechanical Systems Physical Sensors: A Review

Advanced plasma processing combined with trench isolation technology for fabrication and fast prototyping of high aspect ratio MEMS in standard silicon wafers

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