LZW-based code compression for VLIW embedded systems

Abstract

We propose a new variable-sized-block method for VLIW code compression. Code compression traditionally works on fixed-sized blocks and its efficiency is limited by the small block size. Branch blocks -instructions between two consecutive possible branch targets -provide larger blocks for code compression. We propose LZW-based algorithms to compress branch blocks. Our approach is fully adaptive and generates coding table on-the-fly during compression and decompression. When encountering a branch target, the coding table is cleared to ensure correctness. Decompression requires only a simple lookup and update when necessary. Our method provides 8 bytes peak decompression bandwidth and 1.82 bytes in average. Compared to Huffman's 1 byte and V2F's 13-bit peak performance, our methods have higher decoding bandwidth and comparable compression ratio. Parallel decompression could also be applied to our methods, which is more suitable for VLIW architecture.

Adaptive object code compression

“…Consider, for example, that the schemes we reference in this paper have targeted the Compaq Alpha [5,6,7], MIPS [20,25], A RISC like abstract machine [4], ARM [14,27], Texas Instruments TMS320C6x [18,26], PowerPC [12,18], i386 [18] and PDP 11 [9]. Each of these machines employ a different Instruction Set Architecture, with a distinct encoding, providing different opportunities for compression.…”

“…The only attempt at applying adaptive techniques to code compression that we are aware of was presented by Lin [18], where LZW was applied to individual basic blocks in VLIW code. The average basic block size in their experiments was reported at 454 bytes and this provided sufficient context for LZW to achieve compression ratios of 83-87%, and a variant of LZW 75%.…”

“…They are orthogonal to the code compaction methods mentioned above. The techniques have been applied at various levels of granularity including an entire program's abstract syntax tree [8], individual procedures [5,6], basic blocks [18], instruction sequences which do not extend beyond a basic block [14], individual cache lines [12,25] and indeed individual instructions [27].…”

Buri

“…Considering the adoption of software-based compression schemes and their drawbacks of program rewriting and CPU/license costs, and the demonstrated efficiencies of hardware accelerators, it seems natural to offload memory compression burdens to the hardware. Surprisingly, hardware-based compression, including general-purpose memory compression proposals [Ekman and Stenstrom 2005;Sardashti and Wood 2013;Tremaine et al 2001], and code compression designs for embedded systems [Lekatsas and Wolf 1998;Lin et al 2004;Wolfe and Chanin 1992], have not been widely adopted in today's systems. 3 To understand this effect, to follow we describe the major challenges of hardware memory compression and their implications on implementation and adoption.…”

A radar data compression method based on autoencoder neural network and range encoding

“…Lossless compression can be further categorized into statistical model-based, dictionary-based, and residualbased algorithms. The statistical model-based compression algorithm is Huffman [1] coding, while the dictionary-based algorithms are LZW [2] and Range Code methods. The representative residual-based algorithm is DPCM [3].…”