M3-SCoPE: Performance Modeling of Multi-Processor Embedded Systems for Fast Design Space Exploration

Posadas, Héctor; Real, Sara; Villar, Eugenio

doi:10.1007/978-1-4419-8837-9_2

Cited by 9 publications

(9 citation statements)

References 35 publications

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“…This kind of simulation allows speeds near functional execution speeds to be achieved with sufficient accuracy, which is optimal for DSE [6]. Additionally, this generation step needs to be done only once for each DSE iteration, which speeds up the DSE loop.…”

Section: Figure 1 Generic Uml/marte Complex Dse Flowmentioning

confidence: 98%

“…In the first stage, a set of model-to-text transformation tools produce a text-based representation of the COMPLEX UML/MARTE model. In the second stage, a framework called SCoPE+, an evolution of SCoPE [6], reads the text-based description and generates the executable and configurable performance model.…”

Section: Generation Of the Performance Modelmentioning

confidence: 99%

“…The original SCoPE infrastructure [6][7] [8] is a framework able to perform fast co-simulation of complex HW/SW embedded systems based on native simulation technology and able to estimate a wide set of performance figures. SCoPE relies on native simulation technology.…”

Section: Scope+mentioning

confidence: 99%

See 2 more Smart Citations

A MDD methodology for specification of embedded systems and automatic generation of fast configurable and executable performance models

Herrera

Posadas

Peñil

et al. 2012

Proceedings of the Eighth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

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This paper presents the COMPLEX UML/MARTE modeling methodology and its related framework for automatic generation of executable performance models. The modeling methodology supports Model-Driven Development (MDD), required by industrial flows, and a novel set of modeling features specifically suitable for Design Space Exploration (DSE), a crucial design activity. The COMPLEX framework has other advantages for DSE. The COMPLEX tooling enables the automatic generation of an executable and configurable model for fast performance analysis without requiring engineering effort. The COMPLEX tooling automates the production of an easily portable text-based representation of the UML/MARTE model. This representation is read by the underlying simulation infrastructure, which automatically builds a fast performance model supporting the evaluation of different configurations of the system. An important aspect of this performance analysis framework is that it supports a system-level text-based front-end, which is produced from the COMPLEX UML/MARTE model, and which avoids the development of SW implementations, HW refinements, or the implementation of HW/SW interfaces. Moreover, neither code regeneration, nor recompilation is required for any DSE iterations, and thus, the time taken in the exploration is mostly due to model simulation.

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Section: Figure 1 Generic Uml/marte Complex Dse Flowmentioning

confidence: 98%

Section: Generation Of the Performance Modelmentioning

confidence: 99%

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A MDD methodology for specification of embedded systems and automatic generation of fast configurable and executable performance models

Herrera

Posadas

Peñil

et al. 2012

Proceedings of the Eighth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

Self Cite

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“…VirtualSoC [53] is a method for the full system simulation of a general purpose CPU and a many-core hardware accelerator using Quick Emulator (QEMU) and SystemC. Virtual system-based approaches have been proposed by [54,55]. COSSIM [56] is a framework for the full system simulation of networking and processing parts of cyber-physical systems (CPS).…”

Section: Related Work On Efficiency Simulationsmentioning

confidence: 99%

Evaluating the Efficiency of Physical and Cryptographic Security Solutions for Quantum Immune IoT

et al. 2018

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Abstract:The threat of quantum-computer-assisted cryptanalysis is forcing the security community to develop new types of security protocols. These solutions must be secure against classical and post-quantum cryptanalysis techniques as well as feasible for all kinds of devices, including energy-restricted Internet of Things (IoT) devices. The quantum immunity can be implemented in the cryptographic layer, e.g., by using recent lattice-based key exchange algorithms NewHope or Frodo, or in the physical layer of wireless communication, by utilizing eavesdropping-resistant secrecy coding techniques. In this study, we explore and compare the feasibility and energy efficiency of selected cryptographic layer and physical layer approaches by applying an evaluation approach that is based on simulation and modeling. In particular, we consider NewHope and Frodo key exchange algorithms as well as novel physical layer secrecy coding approach that is based on polar codes. The results reveal that our proposed physical layer implementation is very competitive with respect to the cryptographic solutions, particularly in short-range wireless communication. We also observed that the total energy consumption is unequally divided between transmitting and receiving devices in all the studied approaches. This may be an advantage when designing security architectures for energy-restricted devices.

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“…A large body of research has been devoted to performance modeling based of high level of abstraction descriptions (e.g., [15][16][17][18]). Starting with RTL hardware simulation, one can try to speed up the system simulation by using higher-level models of the same circuits, or one can start directly from high-level design to get to the hardware implementation in an iterative process.…”

Section: Functional Simulationmentioning

confidence: 99%

Performance Analysis Techniques for Multi-Soft-Core and Many-Soft-Core Systems

Castells-Rufas

Fernandez-Alonso

Carrabina

2012

International Journal of Reconfigurable Computing

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Multi-soft-core systems are a viable and interesting solution for embedded systems that need a particular tradeoff between performance, flexibility and development speed. As the growing capacity allows it, many-soft-cores are also expected to have relevance to future embedded systems. As a consequence, parallel programming methods and tools will be necessarily embraced as a part of the full system development process. Performance analysis is an important part of the development process for parallel applications. It is usually mandatory when you want to get a desired performance or to verify that the system is meeting some real-time constraints. One of the usual techniques used by the HPC community is the postmortem analysis of application traces. However, this is not easily transported to the embedded systems based on FPGA due to the resource limitations of the platforms. We propose several techniques and some hardware architectural support to be able to generate traces on multiprocessor systems based on FPGAs and use them to optimize the performance of the running applications.

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M3-SCoPE: Performance Modeling of Multi-Processor Embedded Systems for Fast Design Space Exploration

Cited by 9 publications

References 35 publications

A MDD methodology for specification of embedded systems and automatic generation of fast configurable and executable performance models

A MDD methodology for specification of embedded systems and automatic generation of fast configurable and executable performance models

Evaluating the Efficiency of Physical and Cryptographic Security Solutions for Quantum Immune IoT

Performance Analysis Techniques for Multi-Soft-Core and Many-Soft-Core Systems

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