Machine Learning Based Prior-Knowledge-Free Calibration for Split Pipelined-SAR ADCs with Open-Loop Amplifiers Achieving 93.7-dB SFDR

Zhang, Tianli; Cao, Yuefeng; Zhang, Shumin; Chen, Chixiao; Ye, Fan; Ren, Junyan

doi:10.1109/esscirc.2019.8902873

Cited by 23 publications

(8 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Finally, the calibrated 4-channel data are merged to the final output of the TI-ADC. An optional neural network calibration (NNC) is also included [40]. The measurement results with and without NNC are shown in Section 4.…”

Section: Optionalmentioning

confidence: 99%

A 2.5-GS/s Four-Way-Interleaved Ringamp-Based Pipelined-SAR ADC with Digital Background Calibration in 28-nm CMOS

et al. 2021

Self Cite

View full text Add to dashboard Cite

A 2.5-GS/s 12-bit four-way time-interleaved pipelined-SAR ADC is presented in 28-nm CMOS. A bias-enhanced ring amplifier is utilized as the residue amplifier to achieve high bandwidth and excellent power efficiency compared with a traditional operational amplifier. A high linearity front-end is proposed to alleviate the non-linearity of the diode for ESD protection in the input PAD. The embedded input buffer can suppress the kickback noise at high input frequencies. A blind background calibration based on digital-mixing is used to correct the mismatches between channels. Additionally, an optional neural network calibration is also provided. The prototype ADC achieves a low-frequency SNDR/SFDR of 51.0/68.0 dB, translating a competitive FoMw of 0.48 pJ/conv.-step at 250 MHz input running at 2.5 GS/s.

show abstract

Section: Optionalmentioning

confidence: 99%

A 2.5-GS/s Four-Way-Interleaved Ringamp-Based Pipelined-SAR ADC with Digital Background Calibration in 28-nm CMOS

et al. 2021

Self Cite

View full text Add to dashboard Cite

show abstract

“…The difference between two channels is used to train the neural network so that the system tends to be linear, while the average value is used as the calibrated output. Specially, the previous work [6] pointed out that the network could be pruned to reduce the scale at the expense of a certain calibration performance, which removed the weights that have little impact on performance. However, this skill is only suitable for offline-training situation, which is not the case in practice.…”

Section: The Related Workmentioning

confidence: 99%

“…In the past decades, numerous calibration techniques have been proposed to improve the performance, which can be sorted into analog calibration [1][2] and digital calibration [3]- [6] according to the operating domain. Among them, the digital calibration is becoming increasingly popular for its high efficiency, stability and flexibility.…”

Section: Introductionmentioning

confidence: 99%

“…In order to optimize this novel calibration technique, this paper presents an improved scheme called partially binarized and fixed neural network (PBFNN). A 14-bit 60 MS/s ADC manufactured in 28-nm process (see [6] for prototype) is used to verify the feasibility of the PBFNN-based calibration. The measurement results show that the proposed calibration scheme helps the ADCs achieve a spurious-free dynamic range (SFDR) of 95.0 dB and an effective number of bit (ENOB) of 10.6 bit.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A Partially Binarized and Fixed Neural Network Based Calibrator for SAR-Pipelined ADCs Achieving 95.0-dB SFDR

Chen

Zhao

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

Self Cite

View full text Add to dashboard Cite

Recently, the neural network has been applied to calibrate the successive-approximation-register and pipelined analog-to-digital converters (SAR-Pipelined ADCs), which requires no prior knowledge. However, the large hardware area of the full-precision neural network (FPNN) limits the promotion of this method. This paper proposes an optimization scheme called partially binarized and fixed neural network (PBFNN) to simplify the hardware through the following mechanisms. First, the multipliers that occupy a considerable area are optimized by binarization. Second, the fixed layer does not require training, hence saving the hardware for backpropagation. A 14-bit 60 MS/s ADC prototyped in 28-nm CMOS process is used to verify the PBFNN-based calibration. The measurement results show that the ADC achieves an SFDR of 95.0 dB and an ENOB of 10.6 bit. Compared with the previous scheme, the SFDR and ENOB are lossless. We also synthesize both schemes in Synopsys Design Compiler with a 28-nm library. The synthesis result indicates that the hardware area is optimized by 71.95%.

show abstract

“…Most conventional calibration algorithms only address one type of error [1][2][3]. And advanced neural network based calibration algorithms are able to compensate for multiple systematic errors simultaneously [4,5]. However, these methods rarely consider compensating the clock jitter because of its randomness.…”

mentioning

confidence: 99%

An analog‐to‐digital converter calibration algorithm with clock jitter compensation based on bidirectional long‐short‐time‐memory

Zeng

Wan

Chen

et al. 2022

Electronics Letters

View full text Add to dashboard Cite

This letter proposes a bidirectional long‐short‐time‐memory (bi‐LSTM)‐based analog‐to‐digital converter (ADC) background calibration method with a clock jitter compensation function. Different from traditional calibration algorithms, the proposed algorithm utilizes the sequence property of the signal by introducing an LSTM network. The network contains three parts, including a linear layer for input encoding, a refine layer for sequence processing, and a linear layer for output decoding. Two ADCs are used to train the network, one of which is the target to be calibrated, that is, a high‐speed high‐resolution ADC, and the other is a low‐speed ultra‐high‐resolution ADC producing the ideal signal. After the training stage, the network can be used as a postprocessor for the target ADC to compensate for the systemic errors and clock jitter, simultaneously. In the experiments, the proposed method is used to calibrate an ADC12D1600RFIUT, realizing the improvement of signal‐to‐noise distortion ratio (SNDR) from 43.41 to 66.82 dB and SFDR from 56.95 to 98.93 dB.

show abstract

Machine Learning Based Prior-Knowledge-Free Calibration for Split Pipelined-SAR ADCs with Open-Loop Amplifiers Achieving 93.7-dB SFDR

Cited by 23 publications

References 5 publications

A 2.5-GS/s Four-Way-Interleaved Ringamp-Based Pipelined-SAR ADC with Digital Background Calibration in 28-nm CMOS

A 2.5-GS/s Four-Way-Interleaved Ringamp-Based Pipelined-SAR ADC with Digital Background Calibration in 28-nm CMOS

A Partially Binarized and Fixed Neural Network Based Calibrator for SAR-Pipelined ADCs Achieving 95.0-dB SFDR

An analog‐to‐digital converter calibration algorithm with clock jitter compensation based on bidirectional long‐short‐time‐memory

Contact Info

Product

Resources

About