Machine Learning for Electronic Design Automation: A Survey

Huang, Guyue; Hu, Jingbo; He, Yifan; Liu, Jialong; Ma, Mingyuan; Shen, Zhaoyang; Wu, Juejian; Xu, Yuanfan; Zhang, Hengrui; Zhong, Kai; Ning, Xuefei; Ma, Yuzhe; Yang, Haoyu; Yu, Bei; Yang, Huazhong; Wang, Yu

doi:10.1145/3451179

Cited by 169 publications

(38 citation statements)

References 148 publications

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“…Although ML techniques emerged as active areas of research within the holistic electronic design automation pipeline (e.g., in design space reduction [5], placement [6], routing [7], testing and verification [8], [9] and in manufacturing), their examination in logic synthesis only recently started to gain attention. Ere to this work, the authors in [10] distinguish a Fig. 1.…”

Section: Introductionmentioning

confidence: 90%

BOiLS: Bayesian Optimisation for Logic Synthesis

Grosnit¹,

Malherbe²,

Tutunov³

et al. 2021

Preprint

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Optimising the quality-of-results (QoR) of circuits during logic synthesis is a formidable challenge necessitating the exploration of exponentially sized search spaces. While expertdesigned operations aid in uncovering effective sequences, the increase in complexity of logic circuits favours automated procedures. Inspired by the successes of machine learning, researchers adapted deep learning and reinforcement learning to logic synthesis applications. However successful, those techniques suffer from high sample complexities preventing widespread adoption.To enable efficient and scalable solutions, we propose BOiLS, the first algorithm adapting modern Bayesian optimisation to navigate the space of synthesis operations. BOiLS requires no human intervention and effectively trades-off exploration versus exploitation through novel Gaussian process kernels and trustregion constrained acquisitions. In a set of experiments on EPFL benchmarks, we demonstrate BOiLS's superior performance compared to state-of-the-art in terms of both sample efficiency and QoR values.

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Section: Introductionmentioning

confidence: 90%

BOiLS: Bayesian Optimisation for Logic Synthesis

Grosnit¹,

Malherbe²,

Tutunov³

et al. 2021

Preprint

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“…However, the reviews and summary have been presented only for the last five years, limited to five key conferences and journals. Another survey [28] summarizes ML-CAD works in a well-tabulated manner covering many abstraction levels in digital/analog design flow. However, there was little focus on challenges and future directions.…”

Section: Reviews Ic Testingmentioning

confidence: 99%

AI/ML Algorithms and Applications in VLSI Design and Technology

Amuru¹,

Vudumula²,

K.³

et al. 2022

Preprint

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An evident challenge ahead for the integrated circuit (IC) industry in the nanometer regime is the investigation and development of methods that can reduce the design complexity ensuing from growing process variations and curtail the turnaround time of chip manufacturing. Conventional methodologies employed for such tasks are largely manual; thus, time-consuming and resource-intensive. In contrast, the unique learning strategies of artificial intelligence (AI) provide numerous exciting automated approaches for handling complex and dataintensive tasks in very-large-scale integration (VLSI) design and testing. Employing AI and machine learning (ML) algorithms in VLSI design and manufacturing reduces the time and effort for understanding and processing the data within and across different abstraction levels via automated learning algorithms. It, in turn, improves the IC yield and reduces the manufacturing turnaround time. This paper thoroughly reviews the AI/ML automated approaches introduced in the past towards VLSI design and manufacturing. Moreover, we discuss the scope of AI/ML applications in the future at various abstraction levels to revolutionize the field of VLSI design, aiming for high-speed, highly intelligent, and efficient implementations.

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“…EDA tools let designers focus on describing function at a high-level using a hardware description language (HDL) like Verilog, without worrying about low-level implementation of the IC. Increasing design complexity and scalability challenges in the design flow has raised interest in machine learning (ML) for EDA [1].…”

Section: Introductionmentioning

confidence: 99%

“…Even the simplest version of this problem, logic minimization, is Σ 2 p -Hard [2,3]. 1 Commercial logic synthesis tools use heuristics developed by academia and industry [4]. State-of-the-art in logic synthesis applies a sequence of logic minimization heuristics to transform a sum-of-products (SOP) or an andinverter-graph (AIG) representation.…”

Section: Introductionmentioning

confidence: 99%

OpenABC-D: A Large-Scale Dataset For Machine Learning Guided Integrated Circuit Synthesis

Chowdhury¹,

Tan²,

Karri³

et al. 2021

Preprint

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Logic synthesis is a challenging and widely-researched combinatorial optimization problem during integrated circuit (IC) design. It transforms a high-level description of hardware in a programming language like Verilog into an optimized digital circuit netlist, a network of interconnected Boolean logic gates, that implements the function. Spurred by the success of ML in solving combinatorial and graph problems in other domains, there is growing interest in the design of MLguided logic synthesis tools. Yet, there are no standard datasets or prototypical learning tasks defined for this problem domain. Here, we describe OpenABC-D, a large-scale, labeled dataset produced by synthesizing open source designs with a leading open-source logic synthesis tool and illustrate its use in developing, evaluating and benchmarking ML-guided logic synthesis. OpenABC-D has intermediate and final outputs in the form of 870,000 And-Inverter-Graphs (AIGs) produced from 1500 synthesis runs plus labels such as the optimized node counts, and delay. We define a generic learning problem on this dataset and benchmark existing solutions for it. The codes related to dataset creation and benchmark models are available at https://github.com/NYU-MLDA/OpenABC.git. The dataset generated is available at https://archive.nyu.edu/handle/2451/63311. 1 Σ 2 p -Hard problems are hard even with access to an oracle solver for NP-complete problems.

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Machine Learning for Electronic Design Automation: A Survey

Cited by 169 publications

References 148 publications

BOiLS: Bayesian Optimisation for Logic Synthesis

BOiLS: Bayesian Optimisation for Logic Synthesis

AI/ML Algorithms and Applications in VLSI Design and Technology

OpenABC-D: A Large-Scale Dataset For Machine Learning Guided Integrated Circuit Synthesis

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