Macro Modeling Approach for Semi-digital Smart Integrated Circuits

Hoseini, Zaniar; Lee, Kye-Shin; Kim, Byung-Gyu

doi:10.1007/978-94-017-8798-7_35

Cited by 3 publications

(2 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Furthermore, the parasitic at the inverting input of the amplifier is always charged to V CM , which prevents charge sharing errors caused by large parasitic at this node [6]. Since the drain terminal of M 2 is fixed to V CM , there is no need of using a high output resistance current mirror (a simple current mirror will work).…”

Section: Proposed Dac Architecturementioning

confidence: 99%

An area efficient 10-bit time mode hybrid DAC with current settling error compensation

Ravikumar

Hoseini

Lee

et al. 2015

2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)

Self Cite

View full text Add to dashboard Cite

This work describes an area efficient 10-bit time mode hybrid DAC with current settling error compensation. The proposed 10-bit hybrid DAC is realized using a current steering DAC for the lower bits conversion and a time mode DAC for the upper bits conversion. The time mode DAC consist of a single capacitor, amplifier, current mirror and several control switches which occupies less area than other DAC architectures. In addition, the time mode DAC error due to improper current settling is suppressed by the pulse width compensation scheme which does not critically increase the area. The proposed DAC is realized using 0.35µm CMOS technology with estimated core area of 0.00463mm 2 , which is less than most of the existing 10-bit DACs. The maximum DNL and INL with error compensation showed 0.5LSB and -0.6LSB, respectively.

show abstract

Section: Proposed Dac Architecturementioning

confidence: 99%

An area efficient 10-bit time mode hybrid DAC with current settling error compensation

Ravikumar

Hoseini

Lee

et al. 2015

2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)

Self Cite

View full text Add to dashboard Cite

show abstract

“…In this work, in order to overcome the limitations of analog integrated circuit design, in particular reducing the design time, a transistor circuit model based design method that can represent the saturation region operation with linear circuit components is proposed. This is similar to the linear circuit model used for time-mode circuits [4] and image processing circuits [5], however the proposed model is more specialized for MOS transistors. Since the proposed design method can replace the non-linear transistor with a linear circuit model, biasing will be simple and straightforward compared to the conventional design method that deals with the transistor as it is.…”

Section: Introductionmentioning

confidence: 99%

Brief Paper: Linearized Transistor Model Based Automated Biasing Scheme for Analog Integrated Circuits

Lacek¹,

Nahra²,

Roter³

et al. 2021

J Multimed Inf Syst

Self Cite

View full text Add to dashboard Cite

This work presents an automated transistor biasing scheme for analog integrated circuits. In order to effectively bias the transistor at a desired operating point, the proposed method uses a linearized transistor circuit model along with the curve fitted expressions obtained from the pre-simulated I-V characteristics of the actual transistor. As a result, the transistor size that leads to the desired operating point can be easily determined without heavily relying on the circuit simulator, which will lead to significant design time reduction. Furthermore, the proposed method is applied to an actual amplifier circuit where the design time based on the proposed biasing method showed 10× faster than the conventional design approach using the circuit simulator.

show abstract

Compact Time-Mode SAR ADC With Capacitor Flipping Bit-Cycling Operation

Hoseini

Lee

2018

2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)

View full text Add to dashboard Cite

Macro Modeling Approach for Semi-digital Smart Integrated Circuits

Cited by 3 publications

References 7 publications

An area efficient 10-bit time mode hybrid DAC with current settling error compensation

An area efficient 10-bit time mode hybrid DAC with current settling error compensation

Brief Paper: Linearized Transistor Model Based Automated Biasing Scheme for Analog Integrated Circuits

Compact Time-Mode SAR ADC With Capacitor Flipping Bit-Cycling Operation

Contact Info

Product

Resources

About