MADmax: A 1080p stereo-to-multiview rendering ASIC in 65 nm CMOS based on image domain warping

Schaffner, Michael; Greisen, Pierre; Heinzle, Simon; Gürkaynak, Frank K.; Kaeslin, Hubert; Smolic, Aljoscha

doi:10.1109/esscirc.2013.6649072

Cited by 6 publications

(1 citation statement)

References 11 publications

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“…Input pixels thus correspond to Gaussian splats in the output image, which are rasterized within a bounding box and accumulated in a frame buffer. Since Gaussians are closed among themselves and under affine transformations, an anti-aliasing filter for the output image sampling grid can be easily incorporated analytically [23].…”

Section: Warp Interpolation and Renderingmentioning

confidence: 99%

Automatic multiview synthesis — Towards a mobile system on a chip

Schaffner

Gürkaynak

Kaeslin

et al. 2015

2015 Visual Communications and Image Processing (VCIP)

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Over the last couple of years, multiview autostereoscopic displays (MADs) have become commercially available which enable a limited glasses-free 3D experience. The main problem of MADs is that they require several (typically 8 or 9) views, while most of the 3D video content is in stereoscopic 3D (S3D) today. In order to bridge this gap, the research community started to devise automatic multiview synthesis (MVS) methods. These algorithms require real-time processing and should be portable to end-user devices to develop their full potential. In this paper, we present a complete hardware system for fully automatic MVS. We give an overview of the algorithmic flow and corresponding hardware architecture, and provide implementation results of a hybrid FPGA/ASIC prototype -which is the first complete hardware system implementing image-domainwarping-based MVS. The proposed hardware IP could be used as a co-processor in a system-on-chip (SoC) targeting 3D TV sets, thereby enabling efficient content generation in real-time.

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Section: Warp Interpolation and Renderingmentioning

confidence: 99%

Automatic multiview synthesis — Towards a mobile system on a chip

Schaffner

Gürkaynak

Kaeslin

et al. 2015

2015 Visual Communications and Image Processing (VCIP)

Self Cite

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System and VLSI Implementation of Phase-based View Synthesis

Huang

Wang

Chen

et al. 2019

ICASSP 2019 - 2019 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)

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A 250-mW 5.4G-Rendered-Pixel/s Realistic Refocusing Processor for High-Performance Five-Camera Mobile Devices

Chen

Yang

Huang

2023

IEEE Open J. Solid-State Circuits Soc.

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Digital refocusing in multi-camera mobile devices is becoming crucial. Realistic refocusing, which is a subset of digital refocusing, provides physically-correct quality; however, its intense computational complexity results in low processing speed and restricts its applicability. Moreover, its complex computation flow requires substantial DRAM bandwidth and a large SRAM area, making it more challenging to implement in hardware. In this paper, we present a high-performance refocusing processor based on a hardware-oriented realistic refocusing algorithm. The proposed compact computation flow saves 92% of the DRAM bandwidth and 32% of the SRAM area without noticeable quality degradation. To support high-performance refocusing, we develop highly paralleled engines for view rendering. They deliver 5.4G rendered-pixel/sec throughput. The hardware accelerator improves the processing speed by 100× to 350× that of the original refocusing algorithm running on a general purpose processor. The chip is fabricated with 40nm CMOS technology and comprises 271KB of SRAM and 2.3M logic gates. The chip processes Full-HD light fields up to 40 frames per second under 250mW power consumption.INDEX TERMS refocus, multi-camera, light field, view synthesis, DRAM bandwidth reduction, high parallelism

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MADmax: A 1080p stereo-to-multiview rendering ASIC in 65 nm CMOS based on image domain warping

Cited by 6 publications

References 11 publications

Automatic multiview synthesis — Towards a mobile system on a chip

Automatic multiview synthesis — Towards a mobile system on a chip

System and VLSI Implementation of Phase-based View Synthesis

A 250-mW 5.4G-Rendered-Pixel/s Realistic Refocusing Processor for High-Performance Five-Camera Mobile Devices

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