Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks

Abstract

Current main memory organizations in embedded and mobile application systems are DRAM dominated. The everincreasing gap between today's processor and memory speeds makes the DRAM subsystem design a major aspect of computer system design. However, the limitations to DRAM scaling and other challenges like refresh provide undesired trade-offs between performance, energy and area to be made by architecture designers. Several emerging NVM options are being explored to at least partly remedy this but today it is very hard to assess the viability of these proposals because the simulations are not fully based on realistic assumptions on the NVM memory technologies and on the system architecture level. In this paper, we propose to use realistic, calibrated STT-MRAM models and a well calibrated cross-layer simulation and exploration framework, named SEAT, to better consider technologies aspects and architecture constraints. We will focus on general purpose/mobile SoC multicore architectures. We will highlight results for a number of relevant benchmarks, representatives of numerous applications based on actual system architecture. The most energy efficient STT-MRAM based main memory proposal provides an average energy consumption reduction of 27% at the cost of 2x the area and the least energy efficient STT-MRAM based main memory proposal provides an average energy consumption reduction of 8% at the around the same area or lesser when compared to DRAM.

A Multilayer High-Speed Magnetic-Tunnel-Junction Magneto-resistive RAM Structure with Read-Disturb-Detection Circuit by Using Nano-Electronics Quantum Dot Cellular Method

“…A "6T-STT MRAM" with 400 mW powers and 45 ns delay was formed in the paper [22] using "500 x" performance for 1 GB density and [23] presented an "MRAM" with 50 nm diameter. [24] applied a fast "gem 5" simulation on "MRAM" and "DRAM" and manifested that we can replace the other memories using magnetic-RAM to reduce power consumption up to '8%' and '27%' at the cost of '2x' the area with 10.4 ns time-delay.…”

A Detailed Study of SOT-MRAM as an Alternative to DRAM Primary Memory in Multi-Core Environment

“…The significant advantage of MRAM devices is scalability, and they do not require any refresh, reducing static power consumption. STT-MRAM has been explored as the main memory in recent research [1], [7] providing promising results. The average speedups of Open and Close Page Tech- niques with a 1.2x configuration, as mentioned in [1], are 2.4% and 2.7%, respectively.…”

A Comprehensive Study of Temperature and Its Effects in SOT-MRAM Devices

“…As the information in the MRAM is stored in a relative orientation of two magnetic layers, separated by a thin oxide tunnel barrier, the memory is intrinsically nonvolatile. Hence, the static power consumption is strongly reduced with respect to SRAM and DRAM [ 1 , 2 ]. Moreover, the MRAM is also complementary metal–oxide–semiconductor (CMOS) compatible.…”