Majority Voting-Based Reduced Precision Redundancy Adders

Ullah, Anees; Reviriego, Pedro; Pontarelli, Salvatore; Maestro, Juan Antonio

doi:10.1109/tdmr.2017.2781186

Cited by 24 publications

(63 citation statements)

References 8 publications

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“…Other approaches [11], [12] acting at RTL are based on the reduction of the numeric precision in the DWC and TMR schemes. The arithmetic units of the additional replicas and the checking/voting modules elaborate and check only the most significant bits of the values in the nominal circuit so that protection is provided only on a subset of the bits, the most relevant ones for the result of the computation.…”

Section: Related Workmentioning

confidence: 99%

A Neural Network Based Fault Management Scheme for Reliable Image Processing

Biasielli

Bolchini

Cassano

et al. 2020

IEEE Trans. Comput.

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Traditional reliability approaches introduce relevant costs to achieve unconditional correctness during data processing. However, many application environments are inherently tolerant to a certain degree of inexactness or inaccuracy. In this paper, we focus on the practical scenario of image processing in space, a domain where faults are a threat, while the applications are inherently tolerant to a certain degree of errors. We first introduce the concept of usability of the processed image to relax the traditional requirement of unconditional correctness, and to limit the computational overheads related to reliability. We then introduce our new flexible and lightweight fault management methodology for inaccurate application environments. A key novelty of our scheme is the utilization of neural networks to reduce the costs associated with the occurrence and the detection of faults. Experiments on two aerospace image processing case studies show overall time savings of 14.89% and 34.72% for the two applications, respectively, as compared with the baseline classical Duplication with Comparison scheme.

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Section: Related Workmentioning

confidence: 99%

A Neural Network Based Fault Management Scheme for Reliable Image Processing

Biasielli

Bolchini

Cassano

et al. 2020

IEEE Trans. Comput.

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“…The idea of producing inexact, acceptable results after the occurrence of a fault has been proposed in the past mainly for Register-Transfer Level (RTL) designs of Digital Signal Processing (DSP) circuits [7], [8]. The purpose of such a redefinition of the error detection paradigm has been used by approximate computing techniques to reduce the overhead introduced by redundancy-based hardening schemes.…”

Section: B Related Workmentioning

confidence: 99%

“…In [7] the error is detected only if the difference between two redundant results is larger than a given threshold. Reduced Precision Redundancy (RPR) is applied to Triple Modular Redundancy (TMR) in [8] in order to define replicas that elaborate only on a subset of the most significant bits processed by the nominal system. All these works measure the impact of approximation on the single processed value (e.g., the single pixel) and at that granularity they decide whether the results are good or not.…”

Section: B Related Workmentioning

confidence: 99%

“…Even if the architecture comprises three replicas (one nominal and two approximated), the proposed scheme does not allow to achieve an approximate TMR as done in [8], where the system provides an approximated result if the nominal pipeline fails. Indeed our redundant pipeline works on an extremely downscaled input image and its output could not be provided as output of the system, already being the quality of the nominal pipeline's output the minimum required by the application designer.…”

Section: The Proposed Fault Detection Schemementioning

confidence: 99%

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An Approximation-based Fault Detection Scheme for Image Processing Applications

Biasielli

Cassano

Miele

2020

2020 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Image processing applications expose an intrinsic resilience to faults. In this application field the classical Duplication with Comparison (DWC) scheme, where output images are discarded as soon as the two replicas' outputs differ for at least one pixel, may be over-conseravative. This paper introduces a novel lightweight fault detection scheme for image processing applications; i) it extends the DWC scheme by substituting one of the two exact replicas with a faster approximated one; and ii) it features a Neural Network-based checker designed to distinguish between usable and unusable images instead of faulty/unfaulty ones. The application of the hardening scheme on a case study has shown an execution time reduction from 27% to 34% w.r.t. the DWC, while guaranteeing a comparable fault detection capability.

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“…Another problem of TMR is its large area which is at least twice of a normal design. To overcome this limitation, a partial adoption of TMR is utilized in [17]. In this approach, only the most significant bits (MSB) block will be triplicated, which however increases the possibility of system failure to more than 50%.…”

Section: Introductionmentioning

confidence: 99%

Self-Repairing Hybrid Adder With Hot-Standby Topology Using Fault-Localization

2020

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Effective self-repairing can be achieved if the fault along with its exact location can be determined. In this paper, a self-repairing hybrid adder is proposed with fault localization. It uses the advantages of ripple carry adder and carry-select adder to reduce the delay and area overhead. The proposed adder reduces the transistor count by 115% to 76.76% as compared to the existing self-checking carryselect adders. Moreover, the proposed design can detect and localize multiple faults. The fault-recovery is achieved by using the hot-standby approach in which the faulty module is replaced by a functioning module at run-time. In case of 3 consecutive faults, the probability of fault recovery has been found to be 96.1% for a 64-bit adder with 8 blocks, where each block has 9 full adders.

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Majority Voting-Based Reduced Precision Redundancy Adders

Cited by 24 publications

References 8 publications

A Neural Network Based Fault Management Scheme for Reliable Image Processing

A Neural Network Based Fault Management Scheme for Reliable Image Processing

An Approximation-based Fault Detection Scheme for Image Processing Applications

Self-Repairing Hybrid Adder With Hot-Standby Topology Using Fault-Localization

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