Making defect avoidance nearly invisible to the user in wafer scale field programmable gate arrays

Chapman, Glenn H.; Dufort, B.

doi:10.1109/dftvs.1996.571980

Cited by 5 publications

(1 citation statement)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Most of the works has exclusively targeted the logic cell array [18,19,20,21,22,23,24]. An in-depth analysis of the techniques proposed to increase FPGA yield is given in [18].…”

Section: Previous Workmentioning

confidence: 99%

Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs

Campregher

Cheung

Constantinides

et al. 2005

Proceedings of the 2005 ACM/SIGDA 13th International Symposium on Field-Programmable Gate Arrays

View full text Add to dashboard Cite

This paper presents an analysis of the potential yield loss in FPGA due to random defects in metal layers. A proven yield model is adapted to target the FPGA interconnect layers in order to predict the manufacturing yield. Defect parameters from the 2003 SIA roadmap are used to investigate the trend in yield loss due to defects in interconnect layers in the future. It is shown that the low yield predicted for the 45nm technology node and beyond is a cause for concern. The potential impact on yield using two different approaches, namely redundant circuits and fault tolerant design, is also presented.

show abstract

“…Most of the works has exclusively targeted the logic cell array [18,19,20,21,22,23,24]. An in-depth analysis of the techniques proposed to increase FPGA yield is given in [18].…”

Section: Previous Workmentioning

confidence: 99%