Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs

Campregher, Nicola; Cheung, Peter Y. K.; Constantinides, George A.; Vasilko, Milan

doi:10.1145/1046192.1046211

Cited by 49 publications

(48 citation statements)

References 21 publications

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“…In some cases fault can also occur after the chip has been manufactured and tested. In our approach the fact that we modify the configuration bit stream in Hardware inside the chip rather than software allow us to handle such faults [2].…”

Section: Proposed Techniquementioning

confidence: 99%

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Design Approach for Fault Tolerance in FPGA Architecture

Meshram¹,

Belorkar²

2011

VLSICS

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Section: Proposed Techniquementioning

confidence: 99%

“…In this paper we propose a new FPGA like architecture which incorporate fault tolerance in the fabric. Various defects may be produced in a VLSI chip during manufacturing [2]. The existence of defects affects yield and ultimately cost.…”

Section: Introductionmentioning

confidence: 99%

Design Approach for Fault Tolerance in FPGA Architecture

Meshram¹,

Belorkar²

2011

VLSICS

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“…Minimizing the yield loss from defects is an ongoing concern and it may be an even greater challenge in future technologies. For FPGAs it has been predicted that the yield in 22 nm CMOS may be 25% lower than in 90 nm CMOS for the same amount of logic [48].…”

Section: Manufacturing Defectsmentioning

confidence: 99%

FPGA Architecture: Survey and Challenges

Kuon

Tessier

Rose

2008

FNT in Electronic Design Automation

330

109

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Field-Programmable Gate Arrays (FPGAs) have become one of the key digital circuit implementation media over the last decade. A crucial part of their creation lies in their architecture, which governs the nature of their programmable logic functionality and their programmable interconnect. FPGA architecture has a dramatic effect on the quality of the final device's speed performance, area efficiency, and power consumption. This survey reviews the historical development of programmable logic devices, the fundamental programming technologies that the programmability is built on, and then describes the basic understandings gleaned from research on architectures. We include a survey of the key elements of modern commercial FPGA architecture, and look toward future trends in the field.

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“…Compared to ASICs, FPGAs have attained a central focus due to their ability to integrate more complex applications, their flexibility and good performance. Considering that FPGAs based on nanotechnology may have a defect rate of 20% [3] [4], propose techniques to avoid these defects is necessary. Several studies examined the effect of redundancy techniques on the performance of FPGAs.…”

Section: Introductionmentioning

confidence: 99%

Impact of defect tolerance techniques on the criticality of a SRAM-based mesh of cluster FPGA

Blanchardon

Chotin-Avot

Mehrez

et al. 2014

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)

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Abstract-As device sizes shrink, circuits are increasingly prone to manufacturing defects. One of the future challenges is to find a way to use a maximum of defected manufactured circuits. One possible approach to this growing problem is to add redundancy to propose defect-tolerant architectures. But, hardware redundancy increases area. In this paper, we propose a method to determine the most critical elements in a SRAMbased Mesh of Clusters FPGA and different strategies to locally insert hardware redundancy. Depending on the criticality, using defect tolerance, area and timing metrics, five different strategies are evaluated on the Mesh of Clusters architecture. We show that using these techniques on a Mesh of Clusters architecture permits to tolerate 4 times more defects than classic hardware redundancy techniques applied on industrial mesh FPGA. With local strategies, we obtain a best trade off between the number of defects bypassed (37.95%), the FPGA area overhead (21.84%) and the critical path delay increase (9.65%).

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Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs

Cited by 49 publications

References 21 publications

Design Approach for Fault Tolerance in FPGA Architecture

Design Approach for Fault Tolerance in FPGA Architecture

FPGA Architecture: Survey and Challenges

Impact of defect tolerance techniques on the criticality of a SRAM-based mesh of cluster FPGA

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