Mamba: Closing the Performance Gap in Productive Hardware Development Frameworks

Jiang, Shunning; Ilbeyi, Berkin; Batten, Christopher

doi:10.1109/dac.2018.8465576

Cited by 17 publications

(5 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…We implemented a 128-bit key-length AES encryptor and 64bit RISC-V core using our LLVM-C2RTL. For the AES encryptor, we implemented the exact algorithm using Chisel [9] (version 3.3) and PyMTL3 [15] with register transfer level modeling. We did not use any library.…”

Section: Discussionmentioning

confidence: 99%

“…While it builds classes and libraries for hardware on Python for high productivity and parameterization, it applies the just-in-time (JIT) compiler for cycle-level simulation and Verilator [19] for RTL simulations like Chisel. With further study [15], to avoid the double verification load when using Verilator as a simulator, researchers improved the host language simulation speed by optimally generating JIT compiler hardware; however, the simulation speed is still orders of magnitude larger than that of Verilator.…”

Section: Related Workmentioning

confidence: 99%

“…In such a situation, as an alternative to conventional HDLs, new software description languages referred to as domain-specific language (DSL) or middle-level synthesis (MLS) that generate conventional HDL codes (verilog or VHDL) are currently garnering considerable attention. In these approaches, users sometimes must be aware of the hardware implementation at or near the register transfer level; however, designing with these approaches is highly efficient because they are less descriptive and their li-braries are highly reusable [9], [10], [11], [12], [13], [14], [15].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

LLVM-C2RTL: C/C++ Based System Level RTL Design Framework Using LLVM Compiler Infrastructure

Sadasue

Isshiki

2023

IPSJ Transactions on System LSI Design Methodology

View full text Add to dashboard Cite

As the scale of digital circuit design increases, design and verification using conventional hardware description languages (HDLs), such as verilog-HDL and VHDL, limit efficiency. Consequently, high level synthesis (HLS), as well as domain specific languages (DSLs), which alternates conventional HDLs, are beginning to garner attention. We proposed a design framework that uses the C language as a register transfer level descriptive language. In this study, we introduced a LLVM compiler infrastructure to extend our previous work, support the C/C++ standard as the input code, and aggressively optimize the circuit design. In addition to supporting a single module generation, we extended our framework to support the hierarchical module description for efficient system design. We demonstrated the conversion of the input of C/C++ code into the verilog code, optimize its logic, and construct pipelined logic to achieve the original behavior in multiple clock cycles. Our framework offers a significantly efficient system-level hardware design and a powerful debugging environment with software development platforms and tool-sets. The generated hardware logic performs as well as or better than hand-written logic using conventional HDLs.

show abstract

Section: Discussionmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

LLVM-C2RTL: C/C++ Based System Level RTL Design Framework Using LLVM Compiler Infrastructure

Sadasue

Isshiki

2023

IPSJ Transactions on System LSI Design Methodology

View full text Add to dashboard Cite

show abstract

“…Simulation infrastructure. We developed a cycle-level simulator as well as a prototype compiler and runtime for GNNE R A T O R. The cycle-level simulator was developed using the PyMTL3 framework [13]. We implemented cycle-level models of all of the Graph Engine and GNNerator Controller components shown in Figure 2 and integrated the cycleaccurate SCALE-Sim simulator [14] for the Dense Engine.…”

Section: Methodsmentioning

confidence: 99%

GNNerator: A Hardware/Software Framework for Accelerating Graph Neural Networks

Stevens¹,

Das²,

Avancha³

et al. 2021

Preprint

View full text Add to dashboard Cite

Graph Neural Networks (GNNs) apply deep learning to inputs represented as graphs. They use fully-connected layers to extract features from the nodes/edges of a graph and aggregate these features using message passing between nodes, thereby combining two distinct computational patterns: dense, regular computations and sparse, irregular computations. To address the computational challenges posed by GNNs, we propose GNNE R A T O R, an accelerator with heterogeneous compute engines optimized for these two patterns. Further, we propose feature-blocking, a novel GNN dataflow that beneficially trades off irregular memory accesses during aggregation for regular memory accesses during feature extraction. We show that GNNE R A T O R achieves speedups of 5.7-37x over an NVIDIA RTX 2080-Ti, and 2.3x-3.8x over HyGCN, a state-of-the-art GNN accelerator.

show abstract

“…To the best of our knowledge, no straightforward way to transform Python code into hardware designs exists. We are aware of several Python-embedded Hardware Description Languages (HDLs), including Amaranth [31], MyHDL [32], and Mamba [33], but their use in SyDR would require vast re-development efforts. Moreover, as we only aim for a partial conversion of SyDR, we need a software framework and a hardware platform that support low-overhead communication between each other and with which a synthesizable hardware design can be attained with minimal re-development efforts.…”

Section: The Pynq Flowmentioning

confidence: 99%

Hard SyDR: A Benchmarking Environment for Global Navigation Satellite System Algorithms

Grenier,

Lei,

Damsgaard

et al. 2024

Sensors

View full text Add to dashboard Cite

A Global Navigation Satellite System (GNSS) is widely used today for both positioning and timing purposes. Many distinct receiver chips are available as Application-Specific Integrated Circuit (ASIC)s off-the-shelf, each tailored to the requirements of various applications. These chips deliver good performance and low energy consumption but offer customers little-to-no transparency about their internal features. This prevents modification, research in GNSS processing chain enhancement (e.g., application of Approximate Computing (AxC) techniques), and design space exploration to find the optimal receiver for a use case. In this paper, we review the GNSS processing chain using SyDR, our open-source GNSS Software-Defined Radio (SDR) designed for algorithm benchmarking, and highlight the limitations of a software-only environment. In return, we propose an evolution to our system, called Hard SyDR to become closer to the hardware layer and access new Key Performance Indicator (KPI)s, such as power/energy consumption and resource utilization. We use High-Level Synthesis (HLS) and the PYNQ platform to ease our development process and provide an overview of their advantages/limitations in our project. Finally, we evaluate the foreseen developments, including how this work can serve as the foundation for an exploration of AxC techniques in future low-power GNSS receivers.

show abstract

Mamba: Closing the Performance Gap in Productive Hardware Development Frameworks

Cited by 17 publications

References 8 publications

LLVM-C2RTL: C/C++ Based System Level RTL Design Framework Using LLVM Compiler Infrastructure

LLVM-C2RTL: C/C++ Based System Level RTL Design Framework Using LLVM Compiler Infrastructure

GNNerator: A Hardware/Software Framework for Accelerating Graph Neural Networks

Hard SyDR: A Benchmarking Environment for Global Navigation Satellite System Algorithms

Contact Info

Product

Resources

About