Managing mutex variables in a cache-coherent shared-memory system for FPGAs

Abstract

Modern FPGAs have the ability to place many processing elements on a single die that can access shared memory. In a multiprocessing system, mutex variables are often used to provide proper synchronization and access to memory locations shared by the processing elements.This paper introduces a novel technique to manage mutex variables in caches for FPGAs, and is compared to an off-theshelf system built mostly by components from an FPGA vendor. Results show that a cache-coherent system using our proposed technique performs more barriers per second than the off-theshelf system with comparable hardware resources while also providing coherent caches.

LEAP Shared Memories: Automating the Construction of FPGA Coherent Memories

“…Since the existing implementations are processor-specialized, their interfaces typically involve memory addresses which are used to denote mutexes. As a result, these implementations may require more area to implement than our logic-integrated locks (as much as 3x in the case of [10].) Existing implementations provide only lock/mutex management, mostly for the implementation of soft-processor atomic operations.…”

“…Like coherence, most efforts at implementing synchronization in FPGAs have occurred in the context of softcores, either to provide synchronization mechanisms among the cores [10] [14] or between the cores and hardware Table IIIa. *** The CS client's cache line size is changed to 128-bit.…”

“…In addition to the shared queue test benchmark, we also compare the throughput of our barrier service with a throughmemory barrier implementation and an existing FPGA-based barrier system, which is implemented using mutexes in coherent soft processors [10]. The three barrier systems are evaluated with 1000 iterations on 8 threads.…”