Manufacturing implementation of 32nm SRAM using ArF immersion with RET

Lee, Sho-Shen; Wu, Chao−Hsin; Huang, Yongfa; Huang, C. C.; Huang, Hung-Fu; Huang, George; Yu, Chun Chi; Hsu, Michael; Shieh, Simon; Hsu, Stephen; Chiao, Te-Feng

doi:10.1117/12.773137

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Lithography Technology For 2nm Technology1

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2009

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“…35) water-based immersion exposure tool, in combination with considerable, yet manageable design rule restrictions and significant resolution enhancement technologies (RET) [3,4] . Without fundamental changes, however, lithography solutions do not exist for 22 nm node along this path.…”

Section: Lithography Technology For 2nm Technologymentioning

confidence: 99%

Challenges of 22 nm and beyond CMOS technology

Huang

Kang

et al. 2009

Sci. China Ser. F-Inf. Sci.

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It is predicted that CMOS technology will probably enter into 22 nm node around 2012. Scaling of CMOS logic technology from 32 to 22 nm node meets more critical issues and needs some significant changes of the technology, as well as integration of the advanced processes. This paper will review the key processing technologies which can be potentially integrated into 22 nm and beyond technology nodes, including double patterning technology with high NA water immersion lithography and EUV lithography, new device architectures, high K/metal gate (HK/MG) stack and integration technology, mobility enhancement technologies, source/drain engineering and advanced copper interconnect technology with ultra-low-k process.

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Section: Lithography Technology For 2nm Technologymentioning

confidence: 99%