Manufacturing issues related to RTP induced overlay errors in a global alignment stepper technology

Buller, J.F.; Farahani, Mostafa; Garg, S.

doi:10.1109/66.484290

Cited by 10 publications

(4 citation statements)

References 6 publications

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“…Reactor scale modeling of pattern effects has shown that adding or removing a layer from the wafer periphery can have drastic effects on temperature nonuniformity and thermal stress [21]. It has also been shown experimentally that the choice of films on the wafer periphery has significant effect on temperature nonuniformity [22] and pattern misregistration [3] and [4], which arises from wafer warpage.…”

Section: B Results and Discussionmentioning

confidence: 99%

“…1(a)] can lead to pattern induced temperature nonuniformity for the product wafer [1], [2]. The resulting across-wafer temperature nonuniformity can then cause nonuniform device performance, as well as thermal stress induced problems such as wafer slip, dislocations, and wafer warpage [3], [4]. The use of equipment simulations is a promising strategy for exploring solutions to these problems [1], but the ability to predict the radiative properties of a patterned wafer at processing temperatures is crucial to the accuracy of the simulation results.…”

Section: Introductionmentioning

confidence: 99%

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The effect of surface roughness on the radiative properties of patterned silicon wafers

Hebb

Jensen²,

Thomas³

1998

IEEE Trans. Semicond. Manufact.

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The radiative properties of patterned silicon wafers have a major impact on the two critical issues in rapid thermal processing (RTP), namely wafer temperature uniformity and wafer temperature measurement. The surface topography variation of the die area caused by patterning and the roughness of the wafer backside can have a significant effect on the radiative properties, but these effects are not well characterized. We report measurements of room temperature reflectance of a memory die, logic die, and various multilayered wafer backsides. The surface roughness of the die areas and wafer backsides is characterized using atomic force microscopy (AFM). These data are subsequently used to assess the effectiveness of thin film optics in providing approximations for the radiative properties of patterned wafers for RTP applications.

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Section: B Results and Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

The effect of surface roughness on the radiative properties of patterned silicon wafers

Hebb

Jensen²,

Thomas³

1998

IEEE Trans. Semicond. Manufact.

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“…Typically, the non-uniform pattern density of the etched film will result in non-uniform stress. Rapid thermal anneals can also induce wafer stress that remains after the wafers return to room temperature [9,10,11].…”

Section: Wafer Stress and Overlaymentioning

confidence: 99%

Ion beams, thermal processes and lithographic challenges

Levinson

Brunner

2014

2014 20th International Conference on Ion Implantation Technology (IIT)

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Among the challenges with which lithographers are currently grappling, the issues of line-edge roughness (LER) and non-linear overlay errors intersect the concerns of ion implantation and thermal process engineers. LER, and the associated metric for contact holes, local critical dimension uniformity (LCDU), must be small to meet the requirements of advanced nodes. Photon shot-noise-induced LER and LCDU diminution, which can benefit from high resist exposure doses, must be balanced with exposure tool throughput requirements for meeting cost targets for Moore's Law. Because very small improvements in LER and LCDU can require substantial increases in resist exposure doses, post-lithographic techniques for reducing LER and LCDU can have sizable salutary impact on overall wafer costs. The impact of LER on circuit performance depends on the spatial frequencies comprising the LER, and the criticality of particular ranges of spatial frequencies may shift as a consequence of transitions to new types of devices. LER can be reduced post-lithographically by using charged particle beams. Non-linear wafer distortions, which can result from thermal processes and the etching of high-stress films, are problematic for overlay control. Correction of non-linear overlay errors requires the use of a large number of alignment sites and overlay measurements, again resulting in a trade-off between process control and wafer cost. The impact of these distortions on overlay can be predicted quantitatively by measurements of out-of-plane wafer warp. Such measurements can be used to develop processes with intrinsically low distortion and for maintaining process control in manufacturing.

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“…The close interplay between thermal processing and overlay misregistration has been well established in the past [1,2]. A great deal of work has focused on the fundamental relationships between thermal gradients and slip generation with a significant amount of work devoted to modeling the behavior [3][4][5].…”

Section: Introductionmentioning

confidence: 99%

Experimental investigation of the rapid thermal process slip window

Shepard

Muth

Macnish

2010

2010 18th International Conference on Advanced Thermal Processing of Semiconductors (RTP)

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Throughout the history of rapid thermal processing the generation and subsequent elimination of crystalline slip has been an ongoing battle. The combination of high temperatures, temperature gradients, and strain rates typically present in RTPIRTA systems often result in the deformation of the silicon substrate which in turn, leads to problems with lithographic overlay. In recent years, the issue has become more troublesome as technologies continue to scale. A number of events have been documented at IBM where qualified, healthy machines have impacted process yield via the permanent (albeit subtle) deformation of product wafers. Even though a strong correlation between RTP, stress/slip, and overlay failure has been established in the past this work was an attempt to investigate the more subtle nature of recent events in an empirical and systematic fashion. To that end a multi-faceted study was conducted with three specific objectives; (I) to elucidate the relationship between process conditions and overlay failure, (2) to develop a robust automated measurement for stress/slip detection, and (3) to use those techniques and results as a basis from which to better define process windows and manufacturing control strategies. Results from this investigation indicated a critical dependence on pyrometer offset deltas at the wafer edge with values as small as +2C found to produce unacceptable levels of stress. In all cases, the temperature offset window was found to be -IOC wide with the exact location of the slip free conditions dependent on the particulars of the processes and the process chamber.

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Manufacturing issues related to RTP induced overlay errors in a global alignment stepper technology

Cited by 10 publications

References 6 publications

The effect of surface roughness on the radiative properties of patterned silicon wafers

The effect of surface roughness on the radiative properties of patterned silicon wafers

Ion beams, thermal processes and lithographic challenges

Experimental investigation of the rapid thermal process slip window

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