Many-Core vs. Many-Thread Machines: Stay Away From the Valley

Guz, Zvika; Bolotin, Evgeny; Keidar, Idit; Kolodny, Avinoam; Mendelson, Avi; Weiser, Uri

doi:10.1109/l-ca.2009.4

Cited by 86 publications

(52 citation statements)

References 9 publications

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“…Others use the terms Many-Core (MC) and Many-Thread (MT) designs [16,23,26,30]. MC designs are "CPU-like," in that they replicate embedded CPU-cores, and emphasize latency reduction through traditional memory hierarchy and other techniques that boost instruction-level parallelism.…”

Section: Projecting Forwardmentioning

confidence: 99%

On the communication complexity of 3D FFTs and its implications for Exascale

Czechowski

Battaglino

McClanahan

et al. 2012

Proceedings of the 26th ACM International Conference on Supercomputing

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This paper revisits the communication complexity of largescale 3D fast Fourier transforms (FFTs) and asks what impact trends in current architectures will have on FFT performance at exascale. We analyze both memory hierarchy traffic and network communication to derive suitable analytical models, which we calibrate against current software implementations; we then evaluate models to make predictions about potential scaling outcomes at exascale, based on extrapolating current technology trends. Of particular interest is the performance impact of choosing high-density processors, typified today by graphics co-processors (GPUs), as the base processor for an exascale system. Among various observations, a key prediction is that although inter-node all-to-all communication is expected to be the bottleneck of distributed FFTs, intra-node communication-expressed precisely in terms of the relative balance among compute capacity, memory bandwidth, and network bandwidth-will play a critical role.

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Section: Projecting Forwardmentioning

confidence: 99%

On the communication complexity of 3D FFTs and its implications for Exascale

Czechowski

Battaglino

McClanahan

et al. 2012

Proceedings of the 26th ACM International Conference on Supercomputing

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“…In a preliminary work [13] we presented the core of the analytical model and the existence of a valley-like behavior. In Section III, we extend this model with power equations and account for performance-power tradeoffs.…”

Section: Related Workmentioning

confidence: 99%

Threads vs. caches: Modeling the behavior of parallel workloads

Guz

Itzhak

Keidar

et al. 2010

2010 IEEE International Conference on Computer Design

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-A new generation of high-performance engines now combine graphics-oriented parallel processors with a cache architecture. In order to meet this new trend, new highlyparallel workloads are being developed. However, it is often difficult to predict how a given application would perform on a given architecture.This paper provides a new model capturing the behavior of such parallel workloads on different multi-core architectures. Specifically, we provide a simple analytical model, which, for a given application, describes its performance and power as a function of the number of threads it runs in parallel, on a range of architectures. We use our model (backed by simulations) to study both synthetic workloads and real ones from the PARSEC suite. Our findings recognize distinctly different behavior patterns for different application families and architectures.

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“…Guz et al [18] presented an analytical model that quantifies the "performance valley" where too many threads can degrade performance because of the resource contention.…”

Section: Related Workmentioning

confidence: 99%

A Novel Cooperative Warp and Thread Block Scheduling Technique for Improving the GPGPU Resource Utilization

Thuan¹,

Choi²,

Kim³

et al. 2017

KIPS Transactions on Computer and Communication Systems

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General-Purpose Graphics Processing Units (GPGPUs) build massively parallel architecture and apply multithreading technology to explore parallelism. By using programming models like CUDA, and OpenCL, GPGPUs are becoming the best in exploiting plentiful thread-level parallelism caused by parallel applications. Unfortunately, modern GPGPU cannot efficiently utilize its available hardware resources for numerous general-purpose applications. One of the primary reasons is the inefficiency of existing warp/thread block schedulers in hiding long latency instructions, resulting in lost opportunity to improve the performance. This paper studies the effects of hardware thread scheduling policy on GPGPU performance. We propose a novel warp scheduling policy that can alleviate the drawbacks of the traditional round-robin policy. The proposed warp scheduler first classifies the warps of a thread block into two groups, warps with long latency and warps with short latency and then schedules the warps with long latency before the warps with short latency. Furthermore, to support the proposed warp scheduler, we also propose a supplemental technique that can dynamically reduce the number of streaming multiprocessors to which will be assigned thread blocks when encountering a high contention degree at the memory and interconnection network. Based on our experiments on a 15-streaming multiprocessor GPGPU platform, the proposed warp scheduling policy provides an average IPC improvement of 7.5% over the baseline round-robin warp scheduling policy. This paper also shows that the GPGPU performance can be improved by approximately 8.9% on average when the two proposed techniques are combined.

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Many-Core vs. Many-Thread Machines: Stay Away From the Valley

Cited by 86 publications

References 9 publications

On the communication complexity of 3D FFTs and its implications for Exascale

On the communication complexity of 3D FFTs and its implications for Exascale

Threads vs. caches: Modeling the behavior of parallel workloads

A Novel Cooperative Warp and Thread Block Scheduling Technique for Improving the GPGPU Resource Utilization

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