MAPIM: Mat Parallelism for High Performance Processing in Non-volatile Memory Architecture

Sim, Joonseop; Kim, Minsu; Kim, Yeseong; Gupta, Saransh; Khaleghi, Behnam; Rosing, Tajana

doi:10.1109/isqed.2019.8697441

Cited by 3 publications

(2 citation statements)

References 25 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…The technology breaks the bottleneck of traditional computer architecture, which is considered a signicant development trend for future breakthroughs in computing power. 3 W. H. Kautz 4 of the Stanford Research Institute rst proposed the concept of computing-in-memory in the 1970s but was unable to implement it due to technical constraints. Early computing-in-memory solutions were usually based on mature CMOS processes.…”

Section: Introductionmentioning

confidence: 99%

Research progress in architecture and application of RRAM with computing-in-memory

et al. 2023

View full text Add to dashboard Cite

show abstract

Section: Introductionmentioning

confidence: 99%

Research progress in architecture and application of RRAM with computing-in-memory

et al. 2023

View full text Add to dashboard Cite

show abstract

“…基于逻辑操作的存内计算代表工作有: University of California, Santa Barbara 的 Pinatubo [48] , Delft University of Technology 的 Scouting Logic [49] 和 XOR/XNOR 存内计算系统 [50] , University of California, San Diego 的 MPIM [51] 和 MAPIM [52] , 具体如下.…”

Section: 基于逻辑操作的存内计算unclassified

Development of processing-in-memory

Mao¹,

Shu²,

Li³

et al. 2021

Sci. Sin.-Inf.

View full text Add to dashboard Cite

With the explosive increase of processed data, data transmission through the bus between CPU and the main memory has become a bottleneck in the traditional von Neumann architecture. On top of this, popular data-intensive workloads, such as neural networks and graph computing applications, have poor data locality, which results in a substantial increase of the cache miss rate. Processing such popular data-intensive workloads hinders the entire system since the data transmission causes long latency and high energy consumption. Processing-in-memory greatly reduces this data transmission by equipping the main memory with computation ability, alleviating the problems of poor performance and high energy consumption caused by a large amount of data and a poor data locality. Processing-in-memory consists of two different approaches. One method involves integrating computation resources into the main memory with high-bandwidth interconnects (i.e., near data computing). The other method consists of employing memory arrays to compute directly (i.e., computing-inmemory). These two approaches have their own advantages and disadvantages, as well as suitable scenarios. In this survey, the birth and development of processing-in-memory is firstly introduced and discussed. Its techniques, ranging from hardware to microarchitecture, are then presented. Furthermore, the challenges faced by processingin-memory are analyzed. Finally, the opportunities that processing-in-memory offers for popular applications are discussed.

show abstract

VCCIM: a voltage coupling based computing-in-memory architecture in 28 nm for edge AI applications

2022

View full text Add to dashboard Cite

MAPIM: Mat Parallelism for High Performance Processing in Non-volatile Memory Architecture

Cited by 3 publications

References 25 publications

Research progress in architecture and application of RRAM with computing-in-memory

Research progress in architecture and application of RRAM with computing-in-memory

Development of processing-in-memory

VCCIM: a voltage coupling based computing-in-memory architecture in 28 nm for edge AI applications

Contact Info

Product

Resources

About