Mapping a Telecommunication Application on a Multiprocessor System-on-Chip

Genius, Daniela; Faure, Etienne; Pouillon, Nicolas

doi:10.1007/978-90-481-9965-5_3

Cited by 11 publications

(10 citation statements)

References 10 publications

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“…In a previous contribution targetting the generation of virtual prototypes for this particular class of applications [13], design and mapping were purely text-based, thus limiting its usage mostly to academic research, and not to engineers more willing to use graphical frameworks. Hardware components had to be either described by hand, which is errorprone, or generated from a Python specification, and thus be practically unreadable and hard to debug or refactor.…”

Section: Introductionmentioning

confidence: 99%

System-level design for communication-centric task farm applications

Genius

Apvrille

2017

2017 12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)

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Abstract-Massively parallel applications such as telecommunication and video streaming have the particularity that a large proportion of the time is spent on accessing communication channels between the tasks, due to contention on the on-chip interconnect. Moreover, the analysis of a given task deployment is often fastidious. Thus, we propose to extend an existing easy-to-use System-level Design methodology to task farm applications. The contribution first concerns adding relevant SysML modeling elements to take into account application code, hardware platforms and deployment constraints. Secondly, new modeling elements -including access techniques to communication channels -must be given a semantics in order to transform models into a well-defined SystemC virtual prototyping MPSoC platform. A telecommunication application serves as an example.

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Section: Introductionmentioning

confidence: 99%

System-level design for communication-centric task farm applications

Genius

Apvrille

2017

2017 12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)

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“…The improvement of throughput obtained in[6] compared to the implementation based on Disydent presented in[3] was a factor of 3.5.…”

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confidence: 88%

“…One packet of the reference application is treated on average every 675 cycles on the platform containing VCI MWMR stats, as opposed to every 563 cycles on the platform shown in [6]; the simulation overhead is thus around 18%. …”

Section: B Dimensioning the Input Channelsmentioning

confidence: 99%

“…In the following, the application was rewritten by using the SoCLib Design Space Explorer DSX [4], to serve as a reference application for massive task farm parallelism; several extensions of DSX were required to take into account the peculiarities [5]. The exhaustive exploration on a platform based on a flat interconnect [6] exposed several bottlenecks.…”

Section: Introductionmentioning

confidence: 99%

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Monitoring communication channels on a shared memory multi-processor system on chip

Genius¹,

Pouillon²

2011

6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)

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To meet performance requirements, streaming applications have been mapped to Multi-Processor System on Chip (MPSoC). The Kahn Process Network (KPN) paradigm is sufficient when dealing with pipeline parallelism, but such pointto-point channels are impractical in the presence of massive task farm parallelism.Multi Writer Multi Reader (MWMR) channels generalize KPN in such a way that multiple writers and multiple readers access the same channel. They are implemented as software channels stored in on-chip memory to accommodate access by hardware and software tasks alike. The price to pay for this implementation is increased traffic to and from memory.Typical representatives are telecommunication applications which may treat hundreds or thousands of flows at a time, where the same chain of treatments is applied to every packet. The latency for this treatment depends on the packet's content, and can thus not be foreseen. Among multiple tasks which access a MWMR channel, the time to obtain a lock is variable. In consequence, fill states of MWMR channels vary heavily and it is crucial to monitor it in order to detect potential bottlenecks. We show how this can be done early in the design process by using SoCLib/DSX.

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“…Hardware is described at several abstraction levels: TLM (Transaction level), CABA (Cycle/Bit Accurate), and RTL (Register Transfer Level). SoCLib also contains a set of performance evaluation tools (Genius et al, 2011). Last but not least, the SoCLib prototyping platform comes with an operating system well adapted to multiprocessor-on-chip (Becoulet, 2009).…”

Section: Simulation Verification and Prototypingmentioning

confidence: 99%

Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design

Genius

Apvrille

2017

Proceedings of the 5th International Conference on Model-Driven Engineering and Software Development

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Abstract:The design methodology of an embedded system should start with a system-level partitioning dividing functions into hardware and software. However, since this partitioning decision is taken at a high level of abstraction, we propose regularly validating the selected partitioning during software development. The paper introduces a new model-based engineering process with a supporting toolkit, first performing system-level partitioning, and then assessing the partitioning choices thus obtained at different levels of abstraction during software design. This assessment shall in particular validate the assumptions made on system-level (e.g. on cache miss rates) that cannot be precisely determined without low-level hardware model. High-level partitioning simulations/verification rely on custom model-checkers and abstract models of software and hardware, while low-level prototyping simulations rely on automatically generated C-POSIX software code executing on a cycle-precise virtual prototyping platform. An automotive case study on an automatic braking application illustrates our complete approach.

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Mapping a Telecommunication Application on a Multiprocessor System-on-Chip

Cited by 11 publications

References 10 publications

System-level design for communication-centric task farm applications

System-level design for communication-centric task farm applications

Monitoring communication channels on a shared memory multi-processor system on chip

Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design

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