Mapping communication layouts to network hardware characteristics on massive-scale blue gene systems

Abstract

For parallel applications running on high-end computing systems, which processes of an application get launched on which processing cores is typically determined at application launch time without any information about the application characteristics. As high-end computing systems continue to grow in scale, however, this approach is becoming increasingly infeasible for achieving the best performance. For example, for systems such as IBM Blue Gene and Cray XT that rely on flat 3D torus networks, process communication often involves network sharing, even for highly scalable applications. This causes the overall application performance to depend heavily on how processes are mapped on the network. In this paper, we first analyze the impact of different process mappings on application performance on a massive Blue Gene/P system. Then, we match this analysis with application communication patterns that we allow applications to describe prior to being launched. The underlying process management system can use this combined information in conjunction with the hardware characteristics of the system to determine the best mapping for the application. Our experiments study the performance of different communication patterns, including 2D and 3D nearest-neighbor communication and structured Cartesian grid communication. Our studies, that scale up to 131,072 cores of the largest BG/P system in the United States (using 80% of the total system size), demonstrate that different process mappings can show significant difference in overall performance, especially on scale. For example, we show that this difference can be as much as 30% for P3DFFT and up to twofold for HALO. Through our proposed model, however, such differences in performance can be avoided so that the best possible performance is always achieved.

Optimization of Mapping Graphs of Parallel Programs Onto Graphs of Distributed Computer Systems by Recurrent Neural Network

“…The traditional topology aware mappings ((Parhami, 2002;Yu, Chung & Moreira, 2006;Balaji, Gupta, Vishnu & Beckman, 2011)) are constructed especially for regular graphs (hypercubes and tori) of distributed computer systems. The proposed neural network algorithms are more universal and can be used for mapping program graphs onto graphs of distributed computer systems with defects of edges and nodes.…”

“…For this reason, the maximum efficiency of information interactions in advanced highperformance CSs is obtained by using regular graphs (,) sss GVE of connections between individual computers (hypercube, torus) (Parhami, 2002;Yu, Chung & Moreira, 2006;Balaji, Gupta, Vishnu & Beckman, 2011). The hypercube structure is described by a graph known as a m-dimensional Boolean cube with a number of nodes 2 m n  .…”

A Multidimensional Configurable Processor Array — Vocalise

“…Process mapping on the network significantly affects application performance. Moreover, communication efficiency might also be changed when operating applications with different network topologies [15].…”

Optimization of the hop-byte metric for effective topology aware mapping

“…Balaji et al analyzed the impact of different process mappings on application performance on a massive Blue Gene/P system [14]. They show that the difference can be around 30% for some applications and can even be two fold for some.…”

“…Recent works [3], [4], [5], [6], [8], [9], [10], [11] have shown substantial communication performance improvement on large parallel machines by suitable assignment of processes or tasks to nodes of the machine. Earlier works on graph embedding are usually not suitable for modern machines because the earlier works used metrics suitable for a store-and-forward communication mechanism.…”