Mapping Embedded Systems onto NoCs - The Traffic Effect on Dynamic Energy Estimation

Abstract

This work addresses the problem of application mapping in networks-on-chip (NoCs). It explores the importance of characterizing network traffic to effectively predict NoC energy consumption. Traffic is seen as an important factor affecting the problem of mapping applications into NoCs having as goal to minimize the total dynamic energy consumption of a complex system-on-a-chip (SoC). Experiments showed that failing to consider the bit transitions influence on traffic inevitably leads to an energy estimation error. This error is proportional to the amount of bit transitions in transmitted packets. In applications that present a large number of packets exchange, the error is propagated, significantly affecting the mapping results. This paper proposes a high-level application model that captures the traffic effect and uses it to describe the behavior of applications. In order to evaluate the quality of the proposed model, a set of embedded systems were described using both, a previously proposed model (that does not capture the traffic effect), and the model proposed here. Comparing the resulting mappings, those derived from the proposed model showed improvements in energy savings with regard to the other model for all experiments. Categories and Subject DescriptorsB.7.1 [Integrated Circuits]: Types and Design Styles -advanced architectures, algorithms implemented in hardware, VLSI (very large scale integration).

Modeling NoC traffic locality and energy consumption with rent's communication probability distribution

“…The constants E link and Erouter used in equation 4 can be obtained from architecture-level power models, such as Orion 2 [9]. For traffic that follows Rent's rule, the model presented above provides a unique advantage over other approaches [8,10,11]. Given the Rent's exponent, the CPD of traffic can be directly obtained from equation 3.…”

NoC Power Estimation at the RTL Abstraction Level

“…As shown in [6], the power consumption of a router may be divided into three components: buffers, control logic and crossbar. Buffers are responsible for the most significant part of power consumption in the router.…”

“…The power consumption related to the storage of new flits is added to the base power consumption. This power consumption is proportional to the number of switching bits between consecutive flits [6]. The buffer switching activity, and therefore its power consumption, is proportional to its reception rate.…”

“…Palma et al [6] make use of a power consumption model based in the network packet transmission switching activity. The proposed NoC power evaluation flow comprises three basic steps.…”

Performance Evaluation of Hierarchical-Torus NoC

“…As a solution, networks on Chips (NoC) have been suggested [2][6] [9] [23]. These on-chip networks inherit features from networks of parallel computers, such as topologies, routing, and switching techniques, in addition to design constraints imposed by chip area and power consumption budget [3][10] [11] [21] in these types of networks.…”