Mapping irregular applications to DIVA, a PIM-based data-intensive architecture

Abstract

Processing-in-memory (PIM) chips that integrate processor logic into memory devices offer a new opportunity for bridging the growing gap between processor and memory speeds, especially for applications with high memory-bandwidth requirements. The Data-IntensiVe Architecture (DIVA) system combines PIM memories with one or more external host processors and a PIM-to-PIM interconnect. DIVA increases memory bandwidth through two mechanisms: (1) performing selected computation in memory, reducing the quantity of data transferred across the processor-memory interface; and (2) providing communication mechanisms called parcels for moving both data and computation throughout memory, further bypassing the processor-memory bus. DIVA uniquely supports acceleration of important irregular applications, including sparse-matrix and pointer-based computations. In this paper, we focus on several aspects of DIVA designed to effectively support such computations at very high performance levels: (1) the memory model and parcel definitions; (2) the PIM-to-PIM interconnect; and, (3) requirements for the processor-to-memory interface. We demonstrate the potential of PIMbased architectures in accelerating the performance of three irregular computations, sparse conjugate gradient, a natural-join database operation and an object-oriented database query.

Implications of a PIM architectural model for MPI

“…Other experimental systems have still relied on a conventional CPU for overall control or centralized processing (e.g. DIVA [11]), or looked to the outside world as an SMP on a chip with message-passing link interfaces between chips (Blue Gene [1]). This paper assumes a newly emerging view of PIMbased supercomputers (Figure 1) [13,15,7].…”

Automatically mapping code on an intelligent memory architecture

“…Many different types of processor in memory or intelligent memory architectures have been proposed, including IRAM [14], Shamrock [13], Raw [24], Smart Memories [16], Imagine [22], FlexRAM [12], Active Pages [19], and DIVA [8] among others. Some of these architecture projects have associated compiler efforts [1,5,8,11,18].…”

“…This type of architecture, which is popularly known as intelligent memory or processor in memory, has been recently proposed for many systems [8,12,13,14,16,19,22,24].…”

“…In this case, intelligent memory chips act as co-processors in memory that execute code when signaled by the host (main) processor. Examples of proposed systems that use this approach are Active Pages [19], DIVA [8], and FlexRAM [12].…”

“…In previous work on these systems [5,8,12,19], the programmer is expected to identify and isolate the code sections to run on the memory processors. This process is time consuming and error prone.…”