Mapping Neural Networks to FPGA-Based IoT Devices for Ultra-Low Latency Processing

Wielgosz, Maciej; Karwatowski, Michał

doi:10.3390/s19132981

Cited by 24 publications

(14 citation statements)

References 27 publications

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“…DL2HDL [2] is a framework for mapping the DNNs on FPGA using Python and MyHDL (a low-level python language used for the FPGA). First, the models must be PyTorch or Keras models transformed into PyTorch models.…”

Section: Related Workmentioning

confidence: 99%

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Generic Design Flow of Pipelined Hardware Implementation of Deep Neural Networks

Tourad¹,

Eleuldj²

2022

INDJCSE

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DNNs (Deep Neural Networks) have solved various deep learning tasks, including classification problems, natural language processing, and speech recognition. However, this success comes with increased computational and memory requirements. Furthermore, recent deep learning research indicates that hardware implementations such as FPGAs (Field Programmable Gate Arrays) are preferable for implementing DNNs, and they fulfill the requirements due to the integrated circuits with programmable logic gates and connections. This technique offers hardware implementation flexibility, which makes it appealing for a wide range of applications, and that flexibility differs from the standard circuit. As a result, FPGAs are becoming increasingly popular as a hardware solution for accelerating systems and processes. This article presents a generic version of the design flow for automatically implementing DNN models on hardware by generating pipelined HDL codes, which can overcome the implementation problem. The article compares the design flow to other recent similar tools. The design flow is validated using a DNN to detect the diabetic patient from the Pima Indians dataset classification. This paper shows a high performance by reducing the latency by 4x the non-pipelined VHDL code and 1000x the software implementation using the TensorFlow framework without affecting the model's accuracy. Also, this design flow can serve in the early prediction of diabetes in the future-finally, a presentation of the conclusion and future works.

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Section: Related Workmentioning

confidence: 99%

“…A hardware device such as FPGAs contains a wide range of resources, including Flip-Flops, Block RAMs (BRAMs), connected Lookup tables (LUTs), and Digital Signal Processing (DSP) blocks [2]. These characteristics indicate that FPGA devices can be reconfigured and customized.…”

Section: Introductionmentioning

confidence: 99%

Generic Design Flow of Pipelined Hardware Implementation of Deep Neural Networks

Tourad¹,

Eleuldj²

2022

INDJCSE

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“…Additionally, because of its great flexibility, the use of special purpose hardware, such as Field Programmable Gate Arrays (FPGAs), is being widely explored to bring DL techniques to end-devices [27], [28]. Consequently, during the last years, multiple tools for mapping neural networks on FPGAs have appeared [29], [30].…”

Section: Related Workmentioning

confidence: 99%

Gated Recurrent Unit Neural Networks for Automatic Modulation Classification With Resource-Constrained End-Devices

et al. 2020

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The continuous increase in the number of mobile and Internet of Things (IoT) devices, as well as in the wireless data traffic they generate, represents an essential challenge in terms of spectral coexistence. As a result, these devices are now expected to make efficient and dynamic use of the spectrum by employing Cognitive Radio (CR) techniques. In this work, we focus on the Automatic Modulation Classification (AMC). AMC is essential to carry out multiple CR techniques, such as dynamic spectrum access, link adaptation and interference detection, aimed at improving communications throughput and reliability and, in turn, spectral efficiency. In recent years, multiple Deep Learning (DL) techniques have been proposed to address the AMC problem. These DL techniques have demonstrated better generalization, scalability and robustness capabilities compared to previous solutions. However, most of these techniques require high processing and storage capabilities that limit their applicability to energy-and computation-constrained end-devices. In this work, we propose a new gated recurrent unit neural network solution for AMC that has been specifically designed for resource-constrained IoT devices. We trained and tested our solution with over-the-air measurements of real radio signals. Our results show that the proposed solution has a memory footprint of 73.5 kBytes, 51.74% less than the reference model, and achieves a classification accuracy of 92.4%.

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“…The first article in this group is entitled “Mapping Neural Networks to FPGA-Based IoT Devices for Ultra-Low Latency Processing” [ 3 ], by Maciej Wielgosz and Michał Karwatowski. This research exploits the power of reconfigurable hardware to implement algorithms that run efficiently thanks to the intrinsic parallelism provided by field programmable gate arrays (FPGA) devices.…”

Section: Summary Of the Contributions In This Special Issuementioning

confidence: 99%

Algorithm and Distributed Computing for the Internet of Things

Gómez–Pulido

Silva

Hara

2020

Sensors

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The ongoing generalization of Internet of Things and its presence and application in multiple fields is generating a large amount of data that can be used to extract knowledge, among other purposes. In this context, algorithmic techniques and efficient computer systems provide an opportunity to successfully address efficient data processing and intelligent data analysis. As a result, multiple services can be improved, resources can be optimized and real-world problems of interest can be solved. This Special Issue on Algorithm and Distributed Computing for the Internet of Things gives the opportunity to know recent advances in the application of modern technologies hardware and software to the Internet of Things.

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Mapping Neural Networks to FPGA-Based IoT Devices for Ultra-Low Latency Processing

Cited by 24 publications

References 27 publications

Generic Design Flow of Pipelined Hardware Implementation of Deep Neural Networks

Generic Design Flow of Pipelined Hardware Implementation of Deep Neural Networks

Gated Recurrent Unit Neural Networks for Automatic Modulation Classification With Resource-Constrained End-Devices

Algorithm and Distributed Computing for the Internet of Things

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