Mapping Spiking Neural Networks on Multi-core Neuromorphic Platforms: Problem Formulation and Performance Analysis

Barchi, Francesco; Urgese, Gianvito; Macii, Enrico; Acquaviva, Andrea

doi:10.1007/978-3-030-23425-6_9

Cited by 4 publications

(4 citation statements)

References 31 publications

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“…In [106,107], Barchi et al propose a design methodology to map SNNs on globally asynchronous and locally synchronous (GALS) multi-core neuromorphic hardware such as SpiNNaker [23]. Authors propose a task placement pipeline to minimize the spike communication between different computing cores.…”

Section: System Software For Performance and Energy Optimizationmentioning

confidence: 99%

“…Summary: Table 3 summarizes these approaches. SentryOS [85] µBrain [20] Throughput, Utilization Compiler and run-time manager Corelet [87] TrueNorth [26] Core Utilization Compiler framework LCompiler [88] Loihi [25] Core Utilization Compiler framework PACMAN [89], [92] SpiNNaker [23] Core Utilization Compiler framework SNN-PP [104], [106,107] SpiNNaker [23] Spike Communication Energy Compiler and run-time manager PyNN [90] SpiNNaker [23], BrainScaleS [22], Loihi [25] Core Utilization Compiler framework…”

Section: System Software For Performance and Energy Optimizationmentioning

confidence: 99%

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Implementing Spiking Neural Networks on Neuromorphic Architectures: A Review

Huynh¹,

Varshika²,

Paul³

et al. 2022

Preprint

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Recently, both industry and academia have proposed several different neuromorphic systems to execute machine learning applications that are designed using Spiking Neural Networks (SNNs). With the growing complexity on design and technology fronts, programming such systems to admit and execute a machine learning application is becoming increasingly challenging. Additionally, neuromorphic systems are required to guarantee real-time performance, consume lower energy, and provide tolerance to logic and memory failures. Consequently, there is a clear need for system software frameworks that can implement machine learning applications on current and emerging neuromorphic systems, and simultaneously address performance, energy, and reliability. Here, we provide a comprehensive overview of such frameworks proposed for both, platform-based design and hardware-software co-design. We highlight challenges and opportunities that the future holds in the area of system software technology for neuromorphic computing.

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Section: System Software For Performance and Energy Optimizationmentioning

confidence: 99%

Section: System Software For Performance and Energy Optimizationmentioning

confidence: 99%

Implementing Spiking Neural Networks on Neuromorphic Architectures: A Review

Huynh¹,

Varshika²,

Paul³

et al. 2022

Preprint

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“…Following are the two critical neuromorphic design issues associated with having more spikes. First, higher spike count leads to an increase in the network congestion (i.e., delay) and energy consumption on the shared interconnect [55]- [57]. Second, it increases the buffer requirement on input and output ports of each crossbar [43], which increases the design cost (area and power) of an RSNN implementation.…”

Section: B Hardware Implementationmentioning

confidence: 99%

Learning in Feedback-driven Recurrent Spiking Neural Networks using full-FORCE Training

Paul¹,

Wagner²,

Das³

2022

Preprint

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Feedback-driven recurrent spiking neural networks (RSNNs) are powerful computational models that can mimic dynamic systems. However, the presence of a feedback loop from the readout to the recurrent layer de-stabilizes the learning mechanism and prevents it from converging. Here, we propose a supervised training procedure for RSNNs, where a second network is introduced only during the training, to provide hint for the target dynamics. The proposed training procedure consists of generating targets for both recurrent and readout layers (i.e., for a full RSNN system). It uses the recursive least square-based First-Order and Reduced Control Error (FORCE) algorithm to fit the activity of each layer to its target. The proposed full-FORCE training procedure reduces the amount of modifications needed to keep the error between the output and target close to zero. These modifications control the feedback loop, which causes the training to converge. We demonstrate the improved performance and noise robustness of the proposed full-FORCE training procedure to model 8 dynamical systems using RSNNs with leaky integrate and fire (LIF) neurons and rate coding. For energy-efficient hardware implementation, an alternative time-to-first-spike (TTFS) coding is implemented for the full-FORCE training procedure. Compared to rate coding, full-FORCE with TTFS coding generates fewer spikes and facilitates faster convergence to the target dynamics.

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“…Although neuromorphic applications that map the brain's functioning principles to digital hardware have been studied in the last 20 years [15], most of these existing application mapping strategies explored their performance characteristics notably in [16], [17], [18], and [19]. However, the performance attribute of this hardware is a measure of its robustness capabilities in the event of single or multiple fault occurrence [20], [21]. As a consequence, finding the most efficient way to map neuromorphic applications to processor cores represents an important optimization challenge with important implications for application performance and reliability.…”

Section: Introductionmentioning

confidence: 99%

Fault-Tolerant Spiking Neural Network Mapping Algorithm and Architecture to 3D-NoC-Based Neuromorphic Systems

Yerima,

Ikechukwu,

Dang

et al. 2023

IEEE Access

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Neuromorphic computing uses spiking neuron network models to solve machine learning problems in a more energy-efficient way when compared to conventional artificial neural networks. However, mapping the various network components to the neuromorphic hardware is not trivial to realize the desired model for an actual simulation. Moreover, neurons and synapses could be affected by noise due to external interference or random actions of other components (i.e., neurons), which eventually lead to unreliable results. This work proposes a fault-tolerant spiking neural network mapping algorithm and architecture to a 3D network-on-chip (NoC)-based neuromorphic system (R-NASH-II) based on a rank and selection mapping mechanism (RSM). The RSM allows the ranking and rapid selection of neurons for fault-tolerant mapping. Evaluation results show that with our proposed mechanism, we could maintain a mapping efficiency of 100% with 20% spare rate and a fault rate (40%) more than in the previous mapping framework. The Monte Carlo simulation evaluation of reliability shows that the RSM mechanism has increased the mean time to failure (MTTF) of the previous mapping technique by 43% on average. Furthermore, the operational availability of the RSM for mapping to a 4 × 4 × 4 (smallest) and 6 × 6 × 6 (largest) NoC is 88% and 67% respectively.

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Mapping Spiking Neural Networks on Multi-core Neuromorphic Platforms: Problem Formulation and Performance Analysis

Cited by 4 publications

References 31 publications

Implementing Spiking Neural Networks on Neuromorphic Architectures: A Review

Implementing Spiking Neural Networks on Neuromorphic Architectures: A Review

Learning in Feedback-driven Recurrent Spiking Neural Networks using full-FORCE Training

Fault-Tolerant Spiking Neural Network Mapping Algorithm and Architecture to 3D-NoC-Based Neuromorphic Systems

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