Mask Defect Specifications with Fail-Bit-Map Analysis

Abstract

A new mask methodology of mask defect specifications by fail-bit-map (FBM) analysis of LSI devices was proposed. In this paper, concept of new mask defect specifications based on the FBM analysis is shown and impacts on LSI devices of mask defects are studied and the new methodology for next generation is applied.The new mask defect specifications were implemented in a gate-level mask with defects programmed into a 0.175µm-rule DRAM fabrication process, as follows, Firstly, the programmed defects varied in terms of the types, locations and sizes were designed into the memory cell area on the 0.175µm-rule DRAM gate-level mask. Secondly, the gate-level mask with programmed defects was fabricated with conventional mask process flow and the actual mask defect sizes were measured. Thirdly, exposures of the gate-level mask were carried out with conventional 0.175µm-rule DRAM process. Finally, the large impacts on CDs caused by mask defect printability on wafers were clarified and FBM analysis was performed to characterize the relationship among the actual mask defect variations, the CD variations and electrical function of 0.175µm-rule DRAM. This relationship can facilitate determination of the mask defect specifications on 0.175µm-rule DRAM and also likely contribute to estimate next-generation defect specifications.According to the results of the above procedure, the mask defect specifications for opaque defects should be generally tighter than those for clear defects in view of the printability on the wafers and the FBM analysis. Nevertheless, the FBM results suggested that current mask inspection sensitivity for clear defects was too high. With the new methodology, in regard to the impacts of mask defects not only on wafer CDs but also on LSI devices, we have succeeded in obtaining useful results for the mask defect specifications.

Mask defect specification in the spacer patterning process by using a fail-bit-map analysis

“…In terms of device fabrication, one of the most important issues for the mask is the defect control. In the conventional single-exposure wafer process, the mask defect printability to the wafer has already been investigated using a fail-bitmap analysis of a DRAM device [4] . However, it is as yet unclear whether the conventional defect printability is applicable to the spacer patterning process.…”