Mass message transmission aware buffer-less packet-circuit switching router for 3D NoC

Xiao, Yu; Li, Li; Zhang, Yuang; Pan, Hongbing; He, Shan

doi:10.1109/icca.2013.6565046

Cited by 2 publications

(4 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The results show that when speaking of maximal clock frequency, the proposal is 1.37 times faster than router of [13]. This also proves that the proposal underperforms the routers of [11] and [16] in terms of maximal clock frequency because we use a disturbed routing and arbitration. However, it allows the router to handle up to seven packets at the same time.…”

Section: A Fpga Based Designsupporting

confidence: 62%

“…We assessed the proposal performance in terms of maximal clock frequency, area, power consumption and bandwidth and compared it with other famous works. Evaluation results prove that concerning clock frequency, the proposal is 1.37 times faster than our preceding work but it underperforms the routers of [11] and [16] because we use a disturbed routing and arbitration. Hardware cost wise, the proposal is 18.27 and 14.33 times smaller than the router of [17] and [18], respectively.…”

Section: B Asic Based Designmentioning

confidence: 66%

“…The results demonstrate that area wise, the proposal outperforms all other designs. The proposal is 1.02, 2.82 and 5.49 times smaller than routers of [11], [13] and [16] respectively. The results show that when speaking of maximal clock frequency, the proposal is 1.37 times faster than router of [13].…”

Section: A Fpga Based Designmentioning

confidence: 99%

“…The design adopts the negative-first turn model routing algorithm and has been implemented in Virtex-5 FPGA. The authors of [16] describe buffer-less router architecture for 3D NoC. Their architecture uses minimal routing and has been implemented in Virtex-4 FPGA.…”

Section: A Fpga Based Designmentioning

confidence: 99%

See 3 more Smart Citations

Design of Efficient Pipelined Router Architecture for 3D Network on Chip

Chemli¹,

Zitouni²,

Coelho³

et al. 2017

ijacsa

View full text Add to dashboard Cite

Abstract-As a relevant communication structure for integrated circuits, Network-on-Chip (NoC) architecture has attracted a range of research topics. Compared to conventional bus technology, NoC provides higher scalability and enhances the system performance for future System-on-Chip (SoC). Divergently, we presented the packet-switching router design for 2D NoC which supports 2D mesh topology. Despite the offered benefits compared to conventional bus technology, NoC architecture faces some limitations such as high cost communication, high power consumption and inefficient router pipeline usage. One of the proposed solutions is 3D design. In this context, we suggest router architecture for 3D mesh NoC, a natural extension of our prior 2D router design. The proposal uses the wormhole switching and employs the turn mod negativefirst routing algorithm Thus, deadlocks are avoided and dynamic arbiter are implemented to deal with the Quality of Service (QoS) expected by the network. We also adduce an optimization technique for the router pipeline stages. We prototyped the proposal on FPGA and synthesized under Synopsys tool using the 28 nm technology. Results are delivered and compared with other famous works in terms of maximal clock frequency, area, power consumption and estimated peak performance.

show abstract

Section: A Fpga Based Designsupporting

confidence: 62%

Section: B Asic Based Designmentioning

confidence: 66%

Section: A Fpga Based Designmentioning

confidence: 99%

Section: A Fpga Based Designmentioning

confidence: 99%

See 2 more Smart Citations

Design of Efficient Pipelined Router Architecture for 3D Network on Chip

Chemli¹,

Zitouni²,

Coelho³

et al. 2017

ijacsa

View full text Add to dashboard Cite

show abstract

New design of Network on Chip Based on Virtual Routers

Chatmen¹,

Baganne²,

Tourki³

2016

IJEECS

View full text Add to dashboard Cite

<p>Network is considered the most convenient way to communicate between different IP integrated into the same chip. Studies have been developed to propose networks with improved performance in terms of latency, power consumption, throughput and quality of service. Most of these networks have been designed based on the 2-dimensional network structure. Recently, with the introduction of the new structure of 3D integrated circuits (3D IC), new works have used this type of circuit to design 3 dimensions on-chip networks. The advantage brought by this new structure is to reduce the average number of hops crossed from the source to the destination, which improves the throughput and the average latency of the network.</p>

show abstract

Mass message transmission aware buffer-less packet-circuit switching router for 3D NoC

Cited by 2 publications

References 9 publications

Design of Efficient Pipelined Router Architecture for 3D Network on Chip

Design of Efficient Pipelined Router Architecture for 3D Network on Chip

New design of Network on Chip Based on Virtual Routers

Contact Info

Product

Resources

About