Massive signal tracing using on-chip DRAM for in-system silicon debug

Abstract

Silicon debug is a major challenge due to continuously increasing design complexity. Traditional debug methods using signal tracing suffer from the limited capacity of on-chip trace buffers that only allow for signal observation during a short time window. We propose a low-cost debug architecture for massive signal tracing in ICs that integrate fast DRAM, such as 2D-ICs with embedded DRAM or 3D-stacked ICs with wide-I/O DRAM dies. The key idea is to use available on-chip DRAM for trace-data storage, which results in a significant increase of the observation window compared to traditional methods that use trace buffers. During a debug session, the entire observation window is divided into intervals and a signature is calculated for each observed interval using a multipleinput signature register. At run time, intervals containing erroneous bits are identified by comparing their signature with pre-calculated "golden" signatures that are stored in the DRAM a priori. Only failing intervals including their time stamp are stored into DRAM, which allows for a more efficient use of the memory, resulting in a larger observation window. The proposed method does not require multiple iterations or intermediate processing steps, hence it can be used during functional testing with minimum time overhead associated with the upload of golden signatures and the download of stored debug data to external equipment. We have created a Verilog RTL model for the proposed architecture, synthesized it using a 45 nm CMOS library, and verified its functionality by simulation. The results show that the observation window can be increased by orders of magnitude compared to prior work at comparable hardware cost.

On-Chip Error Detection Reusing Built-In Self-Repair for Silicon Debug

“…These CSs are generated completely during the last DI of DS. Moreover, they are compared to the corresponding GCSs using CAMs by the sequence of a cycle, and the comparison result is obtained as a bit (lines [22][23][24][25][26]. This bit is called the child tag bit (CT) in this paper.…”

“…2(a) shows an overview of the DRAM-based silicon debug process. In [23], only the erroneous interval debug data are captured using the MISR signature. First, golden MISR signatures are generated to detect whether the debug interval is erroneous or not; moreover, they are stored in the DRAM using a trace port such as JTAG.…”

“…Finally, the proposed DfD architecture that reuses BISR is described to explain how to reuse BISR. For ready reference, the notations used herein are presented in Table I; these notations are similar to those used in [23].…”

“…This method enables remarkable improvements in the observability of FPGA prototypes. In [23], a massive signal tracing method using an on-chip DRAM, which can be integrated in the 3D-IC, has been introduced. This method detects erroneous debug intervals using a multiple-input signature register (MISR) and stores the error-suspect debug data dump in the DRAM through the trace and shadow buffer.…”

“…The proposed silicon debug method using such conventional BISRs is aimed to improving the quality of error detection by using shorter debug interval detection and reducing the buffer size, DRAM usage, and total debug time. In addition, it is important to note that a cycleaccurate deterministic debug environment is not an impractical assumption [15]- [18], [23]- [28]. Typically, the silicon debug comprises two phases: nondeterministic and deterministic.…”