Massively Parallel Huffman Decoding on GPUs

Weißenberger, André; Schmidt, Bertil

doi:10.1145/3225058.3225076

Cited by 25 publications

(26 citation statements)

References 15 publications

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“…In order to address the limitation of decompression accelerating, the technique for parallel decoding has been researched [ 24 , 25 , 26 , 27 ]. Jang et al [ 25 ] proposed speculative parallelization for deflate decompression.…”

Section: Related Workmentioning

confidence: 99%

“…By applying the parallel decoding to both LZ77 and Huffman code, the authors achieved the increase of decompression throughputs over 13 GB/s on the GPU. Weißenberger et al [ 27 ] presented a GPU-based parallel decoder for Huffman code, which is compatible with the original deflate data format. The authors utilized the self-synchronization property that the decoding process is synchronized after the block boundary.…”

Section: Related Workmentioning

confidence: 99%

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Lossless Decompression Accelerator for Embedded Processor with GUI

Hwang

Cho

et al. 2021

Micromachines

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The development of the mobile industry brings about the demand for high-performance embedded systems in order to meet the requirement of user-centered application. Because of the limitation of memory resource, employing compressed data is efficient for an embedded system. However, the workload for data decompression causes an extreme bottleneck to the embedded processor. One of the ways to alleviate the bottleneck is to integrate a hardware accelerator along with the processor, constructing a system-on-chip (SoC) for the embedded system. In this paper, we propose a lossless decompression accelerator for an embedded processor, which supports LZ77 decompression and static Huffman decoding for an inflate algorithm. The accelerator is implemented on a field programmable gate array (FPGA) to verify the functional suitability and fabricated in a Samsung 65 nm complementary metal oxide semiconductor (CMOS) process. The performance of the accelerator is evaluated by the Canterbury corpus benchmark and achieved throughput up to 20.7 MB/s at 50 MHz system clock frequency.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Lossless Decompression Accelerator for Embedded Processor with GUI

Hwang

Cho

et al. 2021

Micromachines

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“…Funasaka et al [9] demonstrated how decompression could be performed very efficiently on GPUs and presented an adaptive loss-less compression method. However, this approach does not closely follow Huffman's method [18].…”

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confidence: 99%

“…Therefore, most of the work mentioned earlier alters Huffman's original method by splitting up the input data into independent chunks which can be compressed and decompressed separately. This method results in poor compression efficiency and is unsuitable for several file formats [18].…”

mentioning

confidence: 99%

“…Weißenberger and Schmidt [18] proposed a massively parallel Huffman decoder on GPUs based on the self-synchronizing property of the Huffman code. The use of this property enables parallel implementations using a large number of computing units at the cost of added complexity due to computation of synchronizing points across data chunks and its effect on overall area and energy efficiency, which is discussed later in Section 4.…”

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confidence: 99%

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Canonical Huffman Decoder on Fine-grain Many-core Processor Arrays

Sarangi

Baas

2021

Proceedings of the 26th Asia and South Pacific Design Automation Conference

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Canonical Huffman codecs have been used in a wide variety of platforms ranging from mobile devices to data centers which all demand high energy efficiency and high throughput. This work presents bit-parallel canonical Huffman decoder implementations on a fine-grain many-core array built using simple RISC-style programmable processors. We develop multiple energy-efficient and area-efficient decoder implementations and the results are compared with an Intel i7-4850HQ and a massively parallel GT 750M GPU executing the corpus benchmarks: Calgary, Canterbury, Artificial, and Large. The many-core implementations achieve a scaled throughput per chip area that is 324× and 2.7× greater on average than the i7 and GT 750M respectively. In addition, the many-core implementations yield a scaled energy efficiency (bytes decoded per energy) that is 24.1× and 4.6× greater than the i7 and GT 750M respectively. CCS CONCEPTS• Mathematics of computing → Coding theory; • Computer systems organization → Multiple instruction, multiple data.

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GPU implementations of deflate encoding and decoding

Takafuji

Nakano

Ito

et al. 2022

Concurrency and Computation

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Summary Deflate coding is a very popular lossless data compression method used in zlib, gzip (GNU zip), and zip, which performs the LZSS compression algorithm with Huffman coding. Deflate encoding and decoding involve sequential operations and their parallel acceleration using a GPU is quite hard. The main purpose of this paper is to present GPU implementations for encoding and decoding of Deflate coding. For efficient GPU implementations of Deflate coding, we have used multiple small hash tables for finding matching subsequences in the dictionary by multiple threads in parallel and applied the Single Kernel Soft Synchronization (SKSS) technique to fully utilize GPU computing resources. We have also adopted Huffman coding with gap arrays to accelerate parallel Huffman decoding. We have evaluated the performance of our GPU implementations using an NVIDIA A100 GPU and compared them with parallel/sequential Deflate encoding and decoding on the Intel X86 multicore CPUs using multiple threads/a single thread. Our GPU implementation of Deflate decoding is 1.66x–8.33x faster than the multiple thread implementation and 4.13x–36.56x faster than the single thread implementation.

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Massively Parallel Huffman Decoding on GPUs

Cited by 25 publications

References 15 publications

Lossless Decompression Accelerator for Embedded Processor with GUI

Lossless Decompression Accelerator for Embedded Processor with GUI

Canonical Huffman Decoder on Fine-grain Many-core Processor Arrays

GPU implementations of deflate encoding and decoding

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