Massively parallel processing approach to fractal image compression with near-optimal coefficient quantization

Palazzari, P.; Coli, M.; Lulli, Guglielmo

doi:10.1016/s1383-7621(98)00037-x

Cited by 10 publications

(13 citation statements)

References 13 publications

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“…The memory bandwidth together arithmetic intensity advantages GPU over CPU. Moreover, our work shows its advantages when compared to expensive parallel architecture as for instance in [8] which uses 512 floating-point processors with performance comparable to our GPU implementation.…”

Section: Resultsmentioning

confidence: 77%

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Toward Real Time Fractal Image Compression Using Graphics Hardware

Erra

2005

Advances in Visual Computing

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Abstract. In this paper, we present a parallel fractal image compression using the programmable graphics hardware. The main problem of fractal compression is the very high computing time needed to encode images. Our implementation exploits SIMD architecture and inherent parallelism of recently graphic boards to speed-up baseline approach of fractal encoding. The results we present are achieved on cheap and widely available graphics boards.

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Section: Resultsmentioning

confidence: 77%

“…Related work has been done concerning the encoding phase on SIMD architecture. In [8] massively parallel processing approach has been used on an APE100/Quadrics SIMD machine. For testing, they used 512 floating point processors, offering a peak power of 25.6 GFLOPS.…”

Section: Fractal Compressionmentioning

confidence: 99%

Toward Real Time Fractal Image Compression Using Graphics Hardware

Erra

2005

Advances in Visual Computing

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“…Chen et al [8] proposed Kick-out method to discard impossible domain blocks based on one -norm in early stage of current range block is used, in this method for the comparison of range and domain blocks normalization of range and domain block is performed. In parallel approach by Palazzari et al [9] the image is divided into blocks each block is processed by the one processor. Each processor executes sequential algorithm on its block and returns the result.…”

Section: Literature Survey For Ficmentioning

confidence: 99%

Discrete Wavelet Transform based Fractal Image Compression using Parallel Approach

Kodgule¹,

Sonkamble²

2015

IJCA

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Fractal based technique for compression is one of the popular methods for compression of videos and images. It has generated much interest due to its promise of high compression ratios at good decompression quality and it enjoys the advantage of very fast decompression and resolution independent decoding .But it suffers from highly computationally intensive encoding process which makes it unsuitable for real time applications. Many approaches have been suggested but they do not satisfy the requirement of low encoding time and high quality reconstructed images. In this paper parallel algorithm for fractal image compression using NVIDIA`s GPGPU is proposed. Also novel discrete wavelet transform based feature detection is used to reduce the number of block comparisons. Experimental results show significant reduction in encoding time and quality of reconstructed images is also good compared to other approaches making this technique suitable for real time applications such as image retrieval, image denoising, Image authentication and encryption, satellite and medical imaging..

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“…an infinite set) and a metric d a measure of distance. A metric is a non-negative real valued function of two points in the space which obeys three requirements [2,11]: 1. d(x, y) = 0 iff x = y 2. d(x, y) = d(y, x) (reflexivity) 3. d(x, y) < d(x, z) + d(z, y) (the triangular inequality)…”

Section: Images and Transformationsmentioning

confidence: 99%

“…Fractal image compression is easily parallelizable; the encoding of each range block is independent of the others. In [11], one example is given. This obvious general approach, treating the range blocks separately in parallel, is carried over in the design presented here.…”

Section: Obvious Parallel Algorithmsmentioning

confidence: 99%

<title>VHDL design for hardware assistance of fractal image compression</title>

Erickson¹,

Shaaban

Hsu

et al. 2000

Visual Communications and Image Processing 2001

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Fractal image compression schemes have several unusual and useful attributes, including resolution independence, high compression ratios, good image quality, and rapid decompression. Despite this, one major difficulty has prevented their widespread adoption: the extremely high computational complexity of compres sion. Fractal image compression algorithms represent an image as a series of con tractive transformations, each of which maps a large domain block to a smaller range block. Given only this set of transformations, it is possible to reconstruct an approximation of the original image by iteratively applying the transformations to an arbitrary image. Compression consists of partitioning the image into range blocks and finding a suitable transformation of a domain block to represent each one. This search for transformations must generally be done using a brute force approach, compar ing successive domain blocks until a suitable match is found. Some algorithmic improvements have been found, but none are adequate to reduce the required compression time to something reasonable for many uses. This thesis presents a new ASIC design which performs a large number of the required comparisons in parallel, yielding a substantial speedup over a program on a general-purpose computer system. This ASIC is designed in VHDL, which may be synthesized to many different target architectures. The design has considerable flexibility which makes it applicable to different images and applications. The design is based around a pipeline of units that each compare one range block with a series of domain blocks which are fed through the pipeline. Com parisons are made to minimize the mean square error (MSE) of a transform given a linear mapping of the intensity values. This is, by far, the most common minimization strategy used in the literature. The speedup provided by this design is estimated to be about 1,000 times for 256 x 256 images divided into 8x8 blocks over a sequential processor given similar implementation technologies. Contents List of Figures iv List of Tables v Glossary vi 3.5.3 Acken's, Irwin's, and Owens's ASIC Architecture Hardware Design Overview 4.1 Goals and overview 4.2 General Notes and Some Conventions 4.3 Primary Components 4.3.1

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Massively parallel processing approach to fractal image compression with near-optimal coefficient quantization

Cited by 10 publications

References 13 publications

Toward Real Time Fractal Image Compression Using Graphics Hardware

Toward Real Time Fractal Image Compression Using Graphics Hardware

Discrete Wavelet Transform based Fractal Image Compression using Parallel Approach

<title>VHDL design for hardware assistance of fractal image compression</title>

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