Matching cache access behavior and bit error pattern for high performance low Vcc L1 cache

Choi, Young Geun; Yoo, Sungjoo; Lee, Sunggu; Ahn, Jung Ho

doi:10.1145/2024724.2024940

Cited by 11 publications

(5 citation statements)

References 19 publications

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“…Techniques based on replacing faulty cache entries [Wilkerson et al 2008;Chishti et al 2009;Ansari et al 2009;Sasan et al 2009] introduce significant overheads due to bypassing and signal rerouting. Likewise, techniques based on simply disabling faulty storage [Wilkerson et al 2008;Abella et al 2009;Choi et al 2011;Khan et al 2013] may provide noticeable performance variation for a given program depending on the faults' location because the distribution of faulty bits is random. Such techniques are shown effective from an average performance perspective and provide functional correctness, but fail to provide any guarantees on available cache size, number of sets, number of ways, etc., thereby making them useless in real-time scenarios where WCET estimation requires full knowledge of the hardware features below to provide strong timing guarantees [Wilhelm et al 2008].…”

Section: State-of-the-art On Low-energy Cache Designsmentioning

confidence: 99%

Hybrid Cache Designs for Reliable Hybrid High and Ultra-Low Voltage Operation

Maric

Abella

Cazorla

et al. 2014

ACM Trans. Des. Autom. Electron. Syst.

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Geometry scaling of semiconductor devices enables the design of ultra-low-cost (e.g., below 1 USD) battery-powered resource-constrained ubiquitous devices for environment, urban life, and body monitoring. These sensor-based devices require high performance to react in front of infrequent particular events as well as extreme energy efficiency in order to extend battery lifetime during most of the time when low performance is required. In addition, they require real-time guarantees. The most suitable technological solution for these devices consists of using hybrid processors able to operate at: (i) high voltage to provide high performance and (ii) near-/subthreshold voltage to provide ultra-low energy consumption. However, the most efficient SRAM memories for each voltage level differ and trading off different SRAM designs is mandatory. This is particularly true for cache memories, which occupy most of the processor's area. In this article, we propose new, simple, single-Vcc-domain hybrid L1 cache architectures suitable for reliable hybrid high and ultra-low voltage operation. In particular, the cache is designed by combining heterogeneous SRAM cell types: some of the cache ways are optimized to satisfy high-performance requirements during high voltage operation, whereas the rest of the ways provide ultra-low energy consumption and reliability during near-/subthreshold voltage operation. We analyze the performance, energy, and power impact of the proposed cache designs when using them to implement L1 caches in a processor. Experimental results show that our hybrid caches can efficiently and reliably operate across a wide range of voltages, consuming little energy at near-/subthreshold voltage as well as providing high performance at high voltage without decreasing reliability levels to provide strong performance guarantees, as required for our target market.

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Section: State-of-the-art On Low-energy Cache Designsmentioning

confidence: 99%

Hybrid Cache Designs for Reliable Hybrid High and Ultra-Low Voltage Operation

Maric

Abella

Cazorla

et al. 2014

ACM Trans. Des. Autom. Electron. Syst.

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“…Likewise, techniques based on disabling faulty cache entries [21], [1], [7] fail to provide strong timing guarantees required for the worst-case execution time (WCET) estimation, as needed for critical applications in our target market [20]. A failure to perform an operation correctly and within a given time may have catastrophic consequences in these environments.…”

Section: Related Workmentioning

confidence: 99%

Efficient Cache Architectures for Reliable Hybrid Voltage Operation Using EDC Codes

Marić¹,

Abella²,

Valero³

2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

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Abstract-Semiconductor technology evolution enables the design of sensor-based battery-powered ultra-low-cost chips (e.g., below 1 C) required for new market segments such as body, urban life and environment monitoring. Caches have been shown to be the highest energy and area consumer in those chips.This paper proposes a novel, hybrid-operation (high Vcc, ultralow Vcc), single-Vcc domain cache architecture based on replacing energy-hungry bitcells (e.g., 10T) by more energy-efficient and smaller cells (e.g., 8T) enhanced with Error Detection and Correction (EDC) features for high reliability and performance predictability. Our architecture is proven to largely outperform existing solutions in terms of energy and area.

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“…First, there have been many studies on SRAM cache architectures for low Vccmin [17][18][19][20][21][22]. In low-Vcc SRAMs, process variation induces bit errors increase.…”

Section: Related Workmentioning

confidence: 99%

Point and discard

Wang

Dong

Xie

2012

Proceedings of the 49th Annual Design Automation Conference

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Technology scaling of SRAM and embedded DRAM is increasingly constrained by limitations such as leakage power and silicon area. Emerging non-volatile memory technologies are considered as the potential SRAM/eDRAM alternatives for last-level caches in terms of energy and area savings. Unfortunately, these non-volatile memory technologies usually have limited write endurance. Even worse, process variation causes some cells to wear out much earlier than others. While state-of-the-art error-tolerant techniques such as ECC can handle transient soft errors, we need a new architecture for non-volatile last-level caches whose reliability is mainly challenged by hard errors. This paper presents Point-and-Discard (PAD), a hard-failure-tolerant architecture for non-volatile caches. PAD has no initial performance penalty and ensures gradual performance overhead with small storage overhead. By adopting PAD, the lifetime of non-volatile caches can be improved by 4.6X over the conventional architecture under a typical process variation condition. 1

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Matching cache access behavior and bit error pattern for high performance low Vcc L1 cache

Cited by 11 publications

References 19 publications

Hybrid Cache Designs for Reliable Hybrid High and Ultra-Low Voltage Operation

Hybrid Cache Designs for Reliable Hybrid High and Ultra-Low Voltage Operation

Efficient Cache Architectures for Reliable Hybrid Voltage Operation Using EDC Codes

Point and discard

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