Matching properties of MOS transistors

The CMOS inverter can be used as an amplifier if properly biased in the transition region of its voltage-transfer characteristics (VTC). In this paper, the design of this amplifier is investigated with its merits and demerits illustrated and with the various trade-offs involved in its design discussed. Specifically, the following performance metrics are discussed quantitatively: gain, area, linearity, maximum allowable swing, bandwidth, stability, noise factor, impedance matching, and slew rate. Also, the effect of process, voltage, and temperature (PVT) variations are investigated. The optimum number of stages corresponding to the minimum area required for achieving a certain voltage gain is determined. The results obtained from the quantitative analysis and the simulation are discussed.

Section: Review On the Design Of Inverter-based Amplifiersmentioning

confidence: 99%

Design of the CMOS inverter‐based amplifier: A quantitative approach

Sharroush

2019

“…Furthermore, the maximum deviation from the ideal output voltage level due to the ±5% tolerance on the channel length of active load transistors is the same ±0.25% error which occurs on 8% of samples. Additionally, the output DC voltage histogram for a tolerance on the threshold voltage of all transistors based on the Pelgrom's model [18] with a Gaussian distribution and 50 iterations is illustrated in Figure 18, in which 6% of samples have the maximum deviation equal to ±0.56% error from the ideal output voltage level.…”

Section: Post Layout Performance Characterizationmentioning

confidence: 99%

Output‐capacitorless segmented low‐dropout voltage regulator with controlled pass transistors

Saberkari

Qaraqanabadi

Shirmohammadli

et al. 2015

SUMMARYThis article presents a low quiescent current output-capacitorless quasi-digital complementary metal-oxidesemiconductor (CMOS) low-dropout (LDO) voltage regulator with controlled pass transistors according to load demands. The pass transistor of the LDO is segmented into two smaller sizes based on a proposed segmentation criterion, which considers the maximum output voltage transient variations due to the load transient to different load current steps to find the suitable current boundary for segmentation. This criterion shows that low load conditions will cause more output variations and settling time if the pass transistor is used in its maximum size. Furthermore, this situation is the worst case for stability requirements of the LDO. Therefore, using one smaller transistor for low load currents and another one larger for higher currents, a proper trade-off between output variations, complexity, and power dissipation is achieved. The proposed LDO regulator has been designed and post-simulated in HSPICE in a 0.18 μm CMOS process to supply a stable load current between 0 and 100 mA with a 40 pF on-chip output capacitor, while consuming 4.8 μA quiescent current. The dropout voltage of the LDO is set to 200 mV for 1.8 V input voltage. The results reveal an improvement of approximately 53% and 25% on the output voltage variations and settling time, respectively.

“…Process variations are particularly important in subthreshold analog design as a consequence of the exponential sensitivity of the drain current to the threshold voltage variations induced by the random dopant fluctuations and oxide thickness variation. A common and simple way to estimate the effect of the process variations is proposed in [21] where the standard deviation of the threshold voltage of a pair of MOS transistors is evaluated as…”

Section: Process Variationsmentioning

confidence: 99%

“…In the proposed voltage reference, V REF is approximated by the difference between the two threshold voltages. For this reason, according to [21], to obtain a good process stability, a large area for both transistors is necessary. However, it is worth to note that (21) takes in account only the process mismatches induced by random variations but neglects the effect of the systematic mismatches such as temperature and stress.…”

Section: Process Variationsmentioning

confidence: 99%

“…Since robustness to process variability improves as the transistor area increases [21], we can gain further advantage by replicating the basic configuration an appropriate amount of times. The number of replicas is evaluated in order to find a proper trade-off among occupied area, power consumption and improvement in process variability.…”

Section: Process Stability Improvementmentioning

confidence: 99%

See 1 more Smart Citation

A picopower temperature‐compensated, subthreshold CMOS voltage reference

Albano

Crupi

Cucchi

et al. 2013

A voltage reference consisting of only two nMOS transistors with different threshold voltages is presented. Measurements performed on 23 samples from a single batch show a mean reference voltage of 275.4 mV. The subthreshold conduction and the low number of transistors enable to achieve a mean power consumption of only 40 pW. The minimum supply voltage is 0.45 V, which coincides with the lowest value reported so far. The mean TC in the temperature range from 0 to 120 C is 105.4 ppm/ C, while the mean line sensitivity is 0.46%/V in the supply voltage range 0.45-1.8 V. The occupied area is 0.018 mm 2 . The power supply rejection rate without any filtering capacitor is À48 dB at 20 Hz and À29.2 dB at 10 kHz. Thanks to large area transistors and to a careful layout, the coefficient of variation of the reference voltage is only 0.62%. We introduce as a new figure of merit, the voltage temperature parameter (VTP), which gives a direct measure of the overall percentage variation of the reference voltage on the typical 2D domain of supply voltage and temperature. For the proposed circuit, the average VTP is 1.70% with a standard deviation of 0.21%. In order to investigate the effect of transistor area on process variability, a 4X replica of the proposed configuration has been fabricated and tested as well. Except for LS, the 4X replica doesn't exhibit any appreciable improvement with respect to the basic voltage reference.