Material Aspects and Challenges for SOI FinFET Integration

Abstract

FinFET is a promising device concept towards the 32 nm CMOS technology node and beyond as it combines the benefits of multigated architecture, intrinsically having superior scaling behavior, with a highly manufacturable process. The present paper will deal with material aspects of the SOI FinFET integration. We investigate scalability, performance and variability of high aspect ratio trigate FinFETs fabricated with 193nm immersion lithography and conventional dry etch. The effect of gate stack conformality on device performance is studied. The use of ion implantation for extension and the selective epitaxial growth of Si to achieve larger contact area on the source/drain areas are discussed from a materials perspective.

Multi-Gate Fin Field-Effect Transistors Junctions Optimization by Conventional Ion Implantation for (Sub-)22 nm Technology Nodes Circuit Applications

“…7) A problematic fin re-crystallization after amorphizing ion implantation, resulting in defect formation and poor dopant activation, is a well-known concern for narrow-fin devices, 14) since it leads to R SD and ðR SD Þ increase and compromises high-speed operation. 15,16) In this work, the comparable low R SD values of optimized singleor double-sided extension I/I devices with those of extension-less devices also indicates that the low-energy implants used here for extension formation improved the fins crystalline integrity/re-crystallization process.…”

“…R SD values were obtained by plotting the resistance R as a function of physical gate length (L g ) and extrapolating it to L g ¼ 0, with R measured at jV DS j ¼ 20 mV and jV GS À V Tlin j ¼ 2 V. With optimized I/I conditions, no resistance penalty is obtained for single-vs double-sided extension I/I. As for the extension-less devices, the better quality, defect-free SEG obtained when starting from undoped fins 12,14,15) means that low R SD values can in this case be obtained with thinner SEG, with margin for further improvement by increasing its growth time (leading to thicker SEG), 18,19) and potentially resulting in less R out variability. 7) A problematic fin re-crystallization after amorphizing ion implantation, resulting in defect formation and poor dopant activation, is a well-known concern for narrow-fin devices, 14) since it leads to R SD and ðR SD Þ increase and compromises high-speed operation.…”

“…However, FinFET parasitics remain a concern, requiring reduction of the series resistance R SD through improved fin morphology and fin doping. 7,[14][15][16] For ion implanted junctions, this issue is greatly aggravated by tilt angle restrictions due to resist shadowing in tight pitch structures. Recently, to reduce non-uniformity of implanted dosage in the fins in an SRAM cell, responsible for characteristic variability degradation, a single-sided ion implantation (I/I) scheme was proposed, reporting stable SRAM operation, but lower drive current compared to the double-sided I/I case due to higher extension resistance.…”

Two- and Three-Dimensional Fully-Depleted Extension-Less Devices for Advanced Logic and Memory Applications

“…Indeed, an important aspect and also key benefit of the extension-less approach lies in the better quality, defectfree SEG [) less total output resistance (R out ) values and variability] that can be expected to be obtained with this approach, where one grows SEG starting from undoped fins. 10,12,14,17,23,24) The results indicate that this extension-less doping approach can be used to obtain devices where having low I OFF values is the most important parameter to target, but it can also be used to build high performing (= high I ON ) devices with additional expected benefit in terms of R OUT . These devices also exhibit excellent SCE behavior with the I D -V G curves in Fig.…”

“…For both architectures, however, the extremely thin body poses new integration challenges, namely for junction engineering and the extendibility of conventional doping techniques such as ion implantation (with tilt angle restrictions due to resist shadowing at tight pitch), parasitics and series resistance (R S=D ) control. 9,10,13,15,20,[23][24][25] Improved morphology of the crystalline-Si (c-Si) body and near zero-tolerance Si loss is required. In this paper, several extension-less strategies for scaled UTBB and FinFET devices are evaluated for improved performance, shortchannel-effects (SCE), and variability control.…”