FinFET is a promising device concept towards the 32 nm CMOS technology node and beyond as it combines the benefits of multigated architecture, intrinsically having superior scaling behavior, with a highly manufacturable process. The present paper will deal with material aspects of the SOI FinFET integration. We investigate scalability, performance and variability of high aspect ratio trigate FinFETs fabricated with 193nm immersion lithography and conventional dry etch. The effect of gate stack conformality on device performance is studied. The use of ion implantation for extension and the selective epitaxial growth of Si to achieve larger contact area on the source/drain areas are discussed from a materials perspective.

We report a comprehensive evaluation and overview of the latest developments and technology challenges of FinFET-based devices. They offer improved electrostatics and steeper sub-threshold slopes, attractive for enabling further CMOS scaling, but can also suffer from higher parasitic resistance and parasitic capacitance for narrow Fin devices. Critical solutions to minimize the impact of the latter are here addressed, demonstrating their viability for replacing planar CMOS devices. Multiple-VT CMOS can be achieved with capping technology, with aggressively scaled Ring Oscillators (RO) and SRAM cells showing excellent performance and matching behavior.

Multigate MOSFET and epi-tip transistors are promising device concepts which are currently actively investigated. Being attractive from the performance point of view they present certain technological challenges. One of them is the difficulty to control poly-gate encapsulation during the HF removal of native SiO 2 prior to the epitaxial Si deposition of raised sourse/drains. Failed poly-Si encapsulation results in the growth of poly-Si during selective epitaxial growth (SEG) of Si, which shortcuts the source/drain areas. Further it might lead to shadowing effects during post epi implantation steps. These issues can be solved by HCl gas phase etch which effectively removes poly-Si with minimal Source/Drain removal. In this paper, we first discuss the HCl gas phase etch selectivity between poly-Si and crystalline Si (c-Si) in the temperature range of 575 -850 0 C as measured on blanket wafers. Further, we show how this selectivity can be implemented in the production scheme of FinFET devices and epi-tip transistors and as a surface preparation for the epi deposition. Difficulties which can arise due to the HCl gas phase etch are also presented and discussed.

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Improving transistor performance by altering the properties of the silicon channel is a key challenge in electronic research; this can be done, for example, by introducing strain in the channel. In this paper, we report a study of the build-in stress due to a transistor's fabrication process, where different materials are deposited at high temperatures and then cooled down. The study is conducted by comparing Finite Element Modeling simulations with experimental structures measured with CBED. It is found that stresses on the order of hundreds megapascals up to one gigapascal can be generated in the channel of structures with typical dimensions in the hundred nanometer range.