Improving transistor performance by altering the properties of the silicon channel is a key challenge in electronic research; this can be done, for example, by introducing strain in the channel. In this paper, we report a study of the build-in stress due to a transistor's fabrication process, where different materials are deposited at high temperatures and then cooled down. The study is conducted by comparing Finite Element Modeling simulations with experimental structures measured with CBED. It is found that stresses on the order of hundreds megapascals up to one gigapascal can be generated in the channel of structures with typical dimensions in the hundred nanometer range.

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