Materials challenges in three-dimensional integrated circuits

Chen, Kuan‐Neng; Tu, King‐Ning

doi:10.1557/mrs.2015.8

Cited by 76 publications

(22 citation statements)

References 7 publications

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“…Applying heat slowly removes vicinal (hydrogen-bonded) silanols by condensation and elimination of water (Equation 2) [25,26]. (1) The silanols can also react with to generate well-defined charge transfer species (as depicted by Equation 2). In fact reactions are essential for metal barrier films to bind to the isolation liner dielectric [27].…”

Section: Resultsmentioning

confidence: 99%

“…This situation is further complicated by the introduction of new materials and integration schemes; for example, the commercial introduction of three dimensional integrated circuits (3D-ICs) has been hindered by reliability challenges, such as stress related failures, resistivity changes, and unexplained early failures [1,2]. The performance demands of such devices appear to conflict with the need for reliability.…”

Section: Introductionmentioning

confidence: 99%

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Dielectric Spectroscopic Detection of Early Failures in 3-D Integrated Circuits

et al. 2015

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The commercial introduction of three dimensional integrated circuits (3D-ICs) has been hindered by reliability challenges, such as stress related failures, resistivity changes, and unexplained early failures. In this paper, we discuss a new RF-based metrology, based on dielectric spectroscopy, for detecting and characterizing electrically active defects in fully integrated 3D devices. These defects are traceable to the chemistry of the insolation dielectrics used in the through silicon via (TSV) construction. We show that these defects may be responsible for some of the unexplained early reliability failures observed in TSV enabled 3D devices.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Dielectric Spectroscopic Detection of Early Failures in 3-D Integrated Circuits

et al. 2015

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“…They found that Joule heating from the powered micro-bumps was transferred horizontally to the bottom of the neighboring un-powered micro-bumps, creating a large temperature gradient on the order of 1000 • C/cm through the un-powered micro-bumps in the neighboring chip, such that the latter failed due to thermomigration. Recently, due to the diameter of micro-bumps being lower than 20 µm, the whole micro-bump has mostly been constituted by IMC after reflow [83]. Previous work about the reliability of micro-bumps has focused on the mechanical properties of the IMC [84] and the comparison of the resistance to EM and TM (thermo-migration) of the IMC to Pb-free solder [85,86].…”

Section: Micro-bump Electromigration and Heat Transfermentioning

confidence: 99%

TSV Technology and High-Energy Heavy Ions Radiation Impact Review

Tian

Liu

2018

Electronics

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Three-dimensional integrated circuits (3D IC) based on TSV (Through Silicon Via) technology is the latest packaging technology with the smallest size and quality. As a result, it can effectively reduce parasitic effects, improve work efficiency, reduce the power consumption of the chip, and so on. TSV-based silicon interposers have been applied in the ground environment. In order to meet the miniaturization, high performance and low-cost requirements of aerospace equipment, the adapter substrate is a better choice. However, the transfer substrate, as an important part of 3D integrated circuits, may accumulate charge due to heavy ion irradiation and further reduce the performance of the entire chip package in harsh space radiation environment or cause it to fail completely. Little research has been carried out until now. This article summarizes the research methods and conclusions of the research on silicon interposers and TSV technology in recent years, as well as the influence of high-energy heavy ions on semiconductor devices. Based on this, a series of research methods to study the effect of high-energy heavy ions on TSV and silicon adapter plates is proposed.Electronics 2018, 7, 112 2 of 29 wafer was invented by M.G Smith et al. [2], which opposite surfaces were connected ohmically to the degenerately doped portions to be electrically connected along the thru-connection. With further research and exploration, 2.5D/3D integration technology with TSV realized integrated circuits with advantages of high interconnection density, high performance, low power consumption, and low cost [3,4]. In addition, the core is widely considered to be the leading technology in the field of high density packaging in the future and is an effective way to break through Moore's Law [5][6][7]. Figure 1. Silicon interposer through electrical copper coating technology production: (a) The construction of through-silicon via on the wafer; (b) The dry film etchant is stuck on the wafer, then exposed and etched; (c) Hole plating and pad fabrication by electroplating methods; (d) The photoresist removing. Adapted with permission from [27], Copyright Elsevier, 2016.

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“…This situation is further complicated by the introduction of new materials and integration schemes; for example, the commercial introduction of three dimensional integrated circuits (3D-ICs) has been hindered by reliability challenges, such as stress related failures, resistivity changes, and unexplained early failures[1, 2]. The performance demands of such devices appear to conflict with the need for reliability.…”

Section: Introductionmentioning

confidence: 99%