Mathematic Modeling and Circuit Implementation on Multi-Valued Memristor

Wang, Xiaoyuan; Zhou, Pengfei; Jin, Chenxi; Wang, Guangyi; Iu, Herbert Ho Ching

doi:10.1109/iscas45731.2020.9180667

Cited by 4 publications

(7 citation statements)

References 25 publications

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“…In this study, we take the voltage‐controlled tri‐state memristor as the research subject, because the current‐controlled memristor research is similar to that of the voltage‐controlled memristor. We present a mathematical model for voltage‐controlled tri‐state memristors based on the way of building a multi‐valued memristor mathematic model first proposed in [21]. The specific q ‐ φ relation of the tri‐state memristor model is described by an asymmetrical piecewise linear function as follows:

\begin{array}{l} left & q = a + b φ + c | φ + e | - d | φ - e | & φ (0) < - e \end{array}

where q and φ are the charge and the flux of the memristor, φ (0) is the initial state of flux, a , b , c , d , e are constant parameters, here e and– e are the turning points of the tri‐valued memristor.…”

Section: Modeling Of a Tri‐state Memristormentioning

confidence: 99%

“…In this study, we take the voltage-controlled tri-state memristor as the research subject, because the currentcontrolled memristor research is similar to that of the voltage-controlled memristor. We present a mathematical model for voltage-controlled tri-state memristors based on the way of building a multi-valued memristor mathematic model first proposed in [21]. The specific q-φ relation of the tri-state memristor model is described by an asymmetrical piecewise linear function as follows:…”

Section: Mathematical Model Of a Voltagecontrolled Tri-state Memristormentioning

confidence: 99%

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Spice modelling of a tri‐state memristor and analysis of its series and parallel characteristics

Wang

Zhang

et al. 2021

IET Circuits, Devices & Syst

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Memristors are passive non-linear circuit components with memory characteristics, and have been recognized as the fourth basic circuit component, along with resistors, capacitors, and inductors. It has been nearly half a century since the conceptualisation of the memristor, and related research has mainly focussed on the two aspects of binary and continuous memristors. However, compared with these two types of memristors, tri-state and multi-state memristors have greater data density per device, with rich dynamics and great potential in logic and chaotic circuit applications. Moreover, previous studies show that the series-parallel connection of memristor generates more diverse circuit behaviours and increased capacity over a single memristor. However, most of this research is based on mathematical analysis, and lack behavioural circuit simulations or experimental validation. Here, the tri-state memristor is proposed and the mathematic and equivalent Spice models of the tri-state memristor is shown. Furthermore, the circuit characteristics are studied with a complete characterisation of its series-parallel behaviours of the tri-state memristor. Simulations are performed with LTSpice, and the results verify the theoretical analysis, which provides a strong experimental basis for the study of combinational memristive circuits.This is an open access article under the terms of the Creative Commons Attribution-NonCommercial-NoDerivs License, which permits use and distribution in any medium, provided the original work is properly cited, the use is non-commercial and no modifications or adaptations are made.

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\begin{array}{l} left & q = a + b φ + c | φ + e | - d | φ - e | & φ (0) < - e \end{array}

Section: Modeling Of a Tri‐state Memristormentioning

confidence: 99%

Section: Mathematical Model Of a Voltagecontrolled Tri-state Memristormentioning

confidence: 99%

Spice modelling of a tri‐state memristor and analysis of its series and parallel characteristics

Wang

Zhang

et al. 2021

IET Circuits, Devices & Syst

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“…Consequently, digital emulators also attract many researchers due to their small area, hardware flexibility, reconfigurability, and ease of programming and control. [13][14][15][16][17][18] In Vijay Ramakrishnan, 14 a double-gated memristor model is presented, and its applications in analog, digital, and neuromorphic circuits are discussed. Camps et al 15 present a purely digital memristor emulator based on a flux-charge model and implemented in a commercial FPGA.…”

Section: Introductionmentioning

confidence: 99%

“…However, the high power consumption and large area of the analog memristor emulator make it unsuitable for large‐scale memristor integration scenarios. Consequently, digital emulators also attract many researchers due to their small area, hardware flexibility, reconfigurability, and ease of programming and control 13–18 . In Vijay Ramakrishnan, 14 a double‐gated memristor model is presented, and its applications in analog, digital, and neuromorphic circuits are discussed.…”

Section: Introductionmentioning

confidence: 99%

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A gate‐tunable memristor emulator for motion detection

Zhang,

Ma,

Shi

et al. 2023

Circuit Theory & Apps

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SummaryWith its low power consumption and small size, the memristor has shown great potential for improving data storage density and computing efficiency. Compared to the dual‐port memristor, greater attention should be paid to researching gate‐tunable memristor for image processing to improve the processing speed and reduce hardware resource consumption. Developing gate‐tunable memristor emulators is highly attractive given the immaturity of current fabrication of the gate‐tunable memristor. This work proposes a digital gate‐tunable memristor emulator based on Raspberry Pi, which addresses the non‐reconfigurability and inflexibility issues of the analog emulators. The proposed emulator can match the behavior of different memristor devices by regulating the gate voltage parameter. Additionally, it can operate at a maximum frequency of 500 MHz. To test the functionality of the proposed emulator, a digital implementation of the memristive circuit for motion detection is designed and verified experimentally. Experiments demonstrate that when moving object detection is performed on a 640 × 350 pixel video stream, low power consumption of 53 mW and a delay of 3.52 μs can be achieved.

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