Mathematical Models for Predicting Pulse Characteristics in Digital Logic Systems

Critical timing r a c e s {hazards) are a potential problem in digital s y s t e m s consisting of a large number of interchangeable modules and r e p l a c eable integrated circuits. These hazards can be minimized by careful design p r o c e d u r e s and r eviews but will still exist due to system c o mplexities. Systems have been proposed for simulating digital networks based on a time-sequenced logical tracing, but these s y s t e m s require much host computer time and input stimuli to thoroughly exercise the system. The basis of the proposed race analysis system is that all critical races result in an improper flip-flop state. Each flip-flop input is traced, from logic element output to input, accumulating delays. Two basic algorithms are required and described to locate the racing of parallel paths on flip-flop inputs. This system requires minimal u s e r inputs and can perform either a statistical or w o r s t case race analysis.

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Mathematical Models for Predicting Pulse Characteristics in Digital Logic Systems

Cited by 3 publications

References 3 publications

Expected value analysis of combinational logic networks

Expected value analysis of combinational logic networks

A digital system modeling philosophy and design language

Race analysis of digital systems without logic simulation

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