Matrix transposition based on TMS320C6678

Gu, Chengfei; Li, Xiangyang; Chang, Wenge; Jia, Gaowei; Tian, Haishan

doi:10.1109/gsmm.2012.6314000

Cited by 9 publications

(7 citation statements)

References 4 publications

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“…The size of each part is 0.5 K × 4 K, and each one is processed by a corresponding core. As mentioned in [10], the speed of EDMA3 corner turning increases with the decrease of Buffer B's column number. However, fewer columns lead more sub-matrixes to store the processed data, which will increase processing complexity of the next module.…”

Section: Parallel Processing Of Imaging Modulementioning

confidence: 78%

Multi-Core DSP Based Parallel Architecture for FMCW SAR Real-Time Imaging

Gu¹,

Chang²,

Li³

et al. 2015

RADIOENGINEERING

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This paper presents an efficient parallel processing architecture using multi-core Digital Signal Processor (DSP) to improve the capability of real-time imaging for Frequency Modulated Continuous Wave Synthetic Aperture Radar (FMCW SAR). With the application of the proposed processing architecture, the imaging algorithm is modularized, and each module is efficiently realized by the proposed processing architecture. In each module, the data processing of different cores is executed in parallel, also the data transmission and data processing of each core are synchronously carried out, so that the processing time for SAR imaging is reduced significantly. Specifically, the time of corner turning operation, which is very time-consuming, is ignored under computationally intensive case. The proposed parallel architecture is applied to a compact Ku-band FMCW SAR prototype to achieve real-time imageries with 34 cm × 51 cm (range × azimuth) resolution.

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Section: Parallel Processing Of Imaging Modulementioning

confidence: 78%

Multi-Core DSP Based Parallel Architecture for FMCW SAR Real-Time Imaging

Gu¹,

Chang²,

Li³

et al. 2015

RADIOENGINEERING

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“…During the realization of the experimental FMCW SAR system, a modern commercial DSP chip is used, according to which the EDMA operation allows the movement of data among internal memory, external memory, and peripherals to occur without intervention from the DPS core [12], i.e., the EDMA operation is capable to move data in parallel with the computation of DSP cores. In [12], EDMA has been used to realize the corner turn.…”

Section: Performing Bulk Rcmc With Edma Technologymentioning

confidence: 99%

“…In [12], EDMA has been used to realize the corner turn. Similarly, the bulk RCMC could be considered the repositioning of the range-compressed data by reading the data from continuous addresses and writing the data into other continuous addresses.…”

Section: Performing Bulk Rcmc With Edma Technologymentioning

confidence: 99%

“…To clarify the practical feasibility of these simplifications, theoretical judgments are carried out in detail based on the premise that no significant distortion of a SAR image is introduced. In addition, the hardware technique, i.e., the enhanced direct data movement (EDMA) [12], is used to perform the bulk RCMC. In this letter, an experimental Ku-band FMCW SAR system is presented, based on which the real-time imaging is carried out.…”

Section: Introductionmentioning

confidence: 99%

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Simplified Real‐Time Imaging Flow for High‐Resolution FMCW SAR

Jia

Buchroithner

Chang

et al. 2015

IEEE Geosci. Remote Sensing Lett.

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This letter considers the feasibility of a simplified real-time imaging flow theoretically for frequency-modulated continuous-wave synthetic aperture radar (FMCW SAR). The simplified imaging flow is based on the range-Doppler algorithm, whereas the simplifications contain absolving the residual-video-phase correction and performing the second-order motion compensation ahead of the range cell migration correction (RCMC). During the analysis, the platform movement within the transmission of a sweep is considered. Moreover, the hardware technique, i.e., the enhanced direct memory access, is used to improve the efficiency of the bulk RCMC. Eventually, the simplified imaging flow is evaluated in terms of quality and efficiency by using real Ku-band FMCW SAR data. The results indicate that the simplified method could produce SAR imagery of high resolution (0.25 m × 0.25 m) in real time, with a speed-up factor of 2.77 comparing with the frequency scaling algorithm.

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“…Each core has 32-kbyte level-1 program (L1P) memory, 32-kbyte level-1 data (L1D) memory, and 512-kbyte local level-2 (L2) memory [5]. In addition, the TI-C6678 has 4-Mbyte multi-core shared memory (MSM) and supports an external extended memory addressing space of up to 8GBytes for massive data storage [6]. The remainder of this paper is outlined as follows: section 2 details the key technology related with our scheme.…”

Section: Introductionmentioning

confidence: 99%

An Optimized Scheme for High-speed Data Interaction Based on TI-C6678 Multi-core DSP

Bao-yu¹,

Xu²,

Niu³

2013

Proceedings of the International Conference on Computer, Networks and Communication Engineering (ICCNCE 2013)

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-The performance of data interaction between different memories has become a significant factor in the complex embedded systems with the huge increase of processing needs, especially between internal chip-on memory and external memory. This paper advances a constructive optimized scheme named global direct memory access (GDMA) for high-speed data interaction in the multi-core digital signal processor (DSP) systems. Furmore, we give important recommendations to actualize software programming optimization of GDMA from three aspects.This scheme is based on the key technique of enhanced direct memory access versions3 (EDMA3), quick direct memory access (QDMA) and internal direct memory access (IDMA). This scheme can enhance the peak speed of data interaction between local memories by 53.8% and 2.5% averagely for some situations using QDMA compared EDMA3. By establishing the bridge memory area, the speed from level-1 data memory to external memory is optimized by 15.3% maximumly. The multi-core DSP system can achieve the performance of high-speed data interaction at around 5GBps to meet user expectations.

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Matrix transposition based on TMS320C6678

Cited by 9 publications

References 4 publications

Multi-Core DSP Based Parallel Architecture for FMCW SAR Real-Time Imaging

Multi-Core DSP Based Parallel Architecture for FMCW SAR Real-Time Imaging

Simplified Real‐Time Imaging Flow for High‐Resolution FMCW SAR

An Optimized Scheme for High-speed Data Interaction Based on TI-C6678 Multi-core DSP

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