Maximizing Power Efficiency with Asymmetric Multicore Systems

Abstract

In computing systems, a CPU is usually one of the largest consumers of energy. For this reason, reducing CPU power consumption has been a hot topic in the past few years in both the academic community and the industry. In the quest to create more power-efficient CPUs, several researchers have proposed an asymmetric multicore architecture that promises to save a significant amount of power while delivering similar performance to conventional symmetric multicore processors. An AMP (asymmetric multicore processor) consists of cores that use the same ISA (instruction set architecture) but deliver different performance and have different power characteristics. Using the same ISA on all cores means that you can run the same binary on all cores and not have to compile your code with a different compiler for each core type. This stands in contrast to heterogeneous-ISA systems, such as IBM's Cell or Intel's Larrabee, where the cores expose different ISAs, so the code must be compiled separately for each core type. Heterogeneous-ISA systems are not the focus of this article. A typical AMP consists of several fast and powerful cores (high clock frequency, complex out-oforder pipeline, high power consumption) and a large number of slower low-power cores (low clock frequency, simple pipeline, low power consumption). Complex and powerful cores are good for running single-threaded sequential applications, because these applications cannot accelerate their performance by spreading the computation across multiple simple cores. Abundant simple cores, on the other hand, are good for running highly scalable parallel applications. Because of performance/power trade-offs between complex and simple cores, it turns out to be a lot more efficient to run a parallel application on a large number of simple cores than on a smaller number of complex cores that consume the same power or fit into the same area. In a similar vein, complex and powerful cores are good for running CPU-intensive applications that effectively use those processors' advanced microarchitectural features, such as out-of-order super-scalar pipelines, advanced branch prediction facilities, and replicated functional units. At the same time, simple and slow cores deliver a better trade-off between energy consumption and performance for memorybound applications that spend a majority of their execution time fetching data from off-chip memory and stalling the processor. An SMP (symmetric multicore processor) includes cores of only one type: either the complex and powerful ones, as in the Intel Xeon and AMD Opteron processors, or the simple and lower-power ones, as in Sun's Niagara. So in terms of providing the optimal performance/power, an SMP is ideally suited for some applications but not all. Having cores of different types in a single processor enables optimizing performance per watt for a wider range of workloads. Having cores of different

Eficiência Energética em Navegação Web usando DVFS

“…O potencial dos processadores assimétricos em economizar energia foi apresentado em [6] através de implementação de estratégias para escalonamento ciente da assimetria do processador usando algoritmos que podem ser aplicados em sistemas reais e usados nos processadores heterogêneos ou assimétricos, sem sobrecarga significativa. O gerenciamento dinâmico de energia foi desenvolvido para reconfigurar dinamicamente o sistema e assim fornecer os serviços solicitados e os níveis de desempenho com um número mínimo de componentes ativos ou uma carga mínima em tais componentes [3].…”

On the maturity of parallel applications for asymmetric multi-core processors

“…Like in other heterogeneous systems, load balancing and scheduling are fundamental challenges that must be addressed to effectively exploit all the resources in AMC platforms [8,9,10,11,12,13]. Mobile applications rely on multi-programmed workloads to balance the load in the system, while supercomputer applications rely on hand-tuned code to extract maximum performance.…”

Scheduling and performance characterization on heterogeneous computing systems

“…Prior work [5,10,32,54,55,60,62,96,97,97,98,100,104,106,111] on optimizing the performance and power efficiency of execution on heterogeneous architectures, regardless of their ISA interface, has shown that the mapping of heterogeneous resources to programs is crucial. Specifically, heterogeneous resources should be allocated to those programs which make the most of their acceleration potential.…”

“…In single-ISA systems performance asymmetry comes from variation of ISA-transparent characteristics, and typically consist of few powerful, large area cores and many smaller and power-efficient cores [60,62]. Single-ISA performance asymmetry is most frequently emulated by varying core clock frequency, preserving software binary compatibility [32,97,98,100]. Shared-ISA architectures extend micro-architectural, single-ISA asymmetry with functional asymmetry: all cores implement a common, basic ISA while few of them extend it with accelerating instructions for executing certain operations accelerated.…”

“…Fedorova [32] presents a TLP specialization method for single-ISA asymmetric systems. The idea is that sequential execution accelerates more efficiently on accelerated cores, whereas parallel phases execute more efficiently on the numerous basic cores to exploit hardware parallelism.…”