Maximum Error-Aware Design of Approximate Array Multipliers

Shirane, Kenta; Yamamoto, Takahiro; Taniguchi, Ittetsu; Hara-Azumi, Yuko; Yamashita, Shigeru; Tomiyama, Hiroyuki

doi:10.1109/isocc47750.2019.9078488

Cited by 4 publications

(1 citation statement)

References 7 publications

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“…Mainly in this project, a reversible multiplier is used for testing using the reversible BILBO logic applied for finding two main faults SAF, MSAF, and MGF faults of the design. Stuck at faults are rare faults that occur in designs and can be more complexes to find the faults whether to zero or one, Multiple stuck at faults also a rare finding of faults in conventional designs and Missing gate fault changes the output of the design, finding these types of faults are the most important nowadays to make fault free system designs [30], [31].…”

Section: System Design and Testing Methodsmentioning

confidence: 99%

Design and testing of systolic array multiplier using fault injecting schemes

Jahagirdar

Rao

2022

Comput. Sci. Inf. Technol.

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Nowadays low power design circuits are major important for data transmission and processing the information among various system designs. One of the major multipliers used for synchronizing the data transmission is the systolic array multiplier, low power designs are mostly used for increasing the performance and reducing the hardware complexity. Among all the mathematical operations, multiplier plays a major role where it processes more information and with the high complexity of circuit in the existing irreversible design. We develop a systolic array multiplier using reversible gates for low power appliances, faults and coverage of the reversible logic are calculated in this paper. To improvise more, we introduced a reversible logic gate and tested the reversible systolic array multiplier using the fault injection method of built-in self-test block observer (BILBO) in which all corner cases are covered which shows 97% coverage compared with existing designs. Finally, Xilinx ISE 14.7 was used for synthesis and simulation results and compared parameters with existing designs which prove more efficiency.

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Section: System Design and Testing Methodsmentioning

confidence: 99%