Maxwell - a 64 FPGA Supercomputer

Baxter, Rob; Booth, Stephen; Bull, Mark; Cawood, Geoff; Perry, James; Parsons, Mark; Simpson, Andrew; Trew, Arthur; McCormick, A.C.; Smart, George; Smart, Rosanna; Cantle, Allan J.; Chamberlain, Roger D.; Genest, G.

doi:10.1109/ahs.2007.71

Cited by 91 publications

(37 citation statements)

References 2 publications

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“…Maxwell [3] used a 2-D torus interconnect between 64 FPGAS to explore whether an FPGA-based cluster could support many types of high-performance computing applications. Each link in the interconnect used a single multi-gigabit transceiver.…”

Section: Related Workmentioning

confidence: 99%

Latency-Optimized Networks for Clustering FPGAs

Bunker

Swanson

2013

2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines

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Abstract-The data-intensive applications that will shape computing in the coming decades require scalable architectures that incorporate scalable data and compute resources and can support random requests to unstructured (e.g., logs) and semi-structured (e.g., large graph, XML) data sets. To explore the suitability of FPGAs for these computations, we are constructing an FPGAbased system with a memory capacity of 512 GB from a collection of 32 Virtex-5 FPGAs spread across 8 enclosures.This paper describes our work in exploring alternative interconnect technologies and network topologies for FPGA-based clusters. The diverse interconnects combine inter-enclosure high-speed serial links and wide, single-ended intra-enclosure on-board traces with network topologies that balance network diameter, network throughput, and FPGA resource usage. We discuss the architecture of high-radix routers in FPGAs that optimize for the asymmetry between the inter-and intra-enclosure links. We analyze the various interconnects that aim to efficiently utilize the prototype's total switching capacity of 2.43 Tb/s. The networks we present have aggregate throughputs up to 51.4 GB/s for random traffic, diameters as low as 845 nanoseconds, and consume less than 12% of the FPGAs' logic resources.

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Section: Related Workmentioning

confidence: 99%

Latency-Optimized Networks for Clustering FPGAs

Bunker

Swanson

2013

2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines

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“…A line of special purpose development boards based on such FPGAs are also available(e.g. Nallatech and Alpha data) which are particularly suitable for HPC; some of these come with tools which help faster algorithm-to-hardware realization with high-level C-like constructs; Maxwell [1,2], a FPGA parallel computer, is a good example of a system built around such hardware/software ecosystem.…”

Section: Introductionmentioning

confidence: 99%

FPGA Based High Performance Double-Precision Matrix Multiplication

Kumar

Joshi

Patkar

et al. 2010

Int J Parallel Prog

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We present two designs (I and II) for IEEE 754 double precision floating point matrix multiplication, optimized for implementation on high-end FPGAs. It forms the kernel in many important tile-based BLAS algorithms, making an excellent candidate for acceleration. The designs, both based on the rank-1 update scheme, can handle arbitrary matrix sizes, and are able to sustain their peak performance except during an initial latency period. Through these designs, the trade-offs involved in terms of local-memory and bandwidth for an FPGA implementation are demonstrated and an analysis is presented for the optimal choice of design parameters. The designs, implemented on a Virtex-5 SX240T FPGA, scale gracefully from 1 to 40 processing elements(PEs) with a less than 1% degradation in the design frequency of 373 MHz. With 40 PEs and a design speed of 373 MHz, a sustained performance of 29.8 GFLOPS is possible with a bandwidth requirement of 750 MB/s for design-II and 5.9 GB/s for design-I. This compares favourably with both related art and general purpose CPU implementations.

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“…Thus, the off-chip bandwidth of VS achieves 3,192 MB/s via six-way channels with 3D connections. This is higher than Maxwell [7], where in the FPGA Board connects to the CPU using a PCI/PCI-X bridge that is capable of 64-bit, 133 MHz operation in PCI-X mode. The configuration has a peak bandwidth of 600 MB/s, which is a potential performance bottleneck for Maxwell.…”

Section: Fpga Arraymentioning

confidence: 99%

“…Many parallel computing systems with multi-FPGAs have been developed, such as Maxwell [7], the Berkeley Emulation Engine (BEE) [8], Cube [9], programmable active memory (PAM) [10], and the systolic computationalmemory array (SCMA) [11]. The third-generation BEE (BEE3) comprises modules with four Virtex-5 FPGAs connected by ring interconnection.…”

Section: Introductionmentioning

confidence: 99%

A Multidimensional Configurable Processor Array — Vocalise

Jiang

Atsumari

Kubo

et al. 2015

IEICE Trans. Inf. & Syst.

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Jiang LI†a) , Student Member, Yusuke ATSUMARI †b) , Hiromasa KUBO †c) , Yuichi OGISHIMA †d) , Satoru YOKOTA †e) , Nonmembers, Hakaru TAMUKOH † †f) , and Masatoshi SEKINE †g) , Members SUMMARY A processing system with multiple field programmable gate array (FPGA) cards is described. Each FPGA card can interconnect using six I/O (up, down, left, right, front, and back) terminals. The communication network among FPGAs is scalable according to user design. When the system operates multi-dimensional applications, transmission efficiency among FPGA improved through user-adjusted dimensionality and network topologies for different applications. We provide a fast and flexible circuit configuration method for FPGAs of a multi-dimensional FPGA array. To demonstrate the effectiveness of the proposed method, we assess performance and power consumption of a circuit that calculated 3D Poisson equations using the finite difference method.

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Maxwell - a 64 FPGA Supercomputer

Cited by 91 publications

References 2 publications

Latency-Optimized Networks for Clustering FPGAs

Latency-Optimized Networks for Clustering FPGAs

FPGA Based High Performance Double-Precision Matrix Multiplication

A Multidimensional Configurable Processor Array — Vocalise

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