MBIST Controller Based on March-ee Algorithm

Alnatheer

2022

Micromachines

Self Cite

Including redundancy is popular and widely used in a fault-tolerant method for memories. Effective fault-tolerant methods are a demand of today’s large-size memories. Recently, system-on-chips (SOCs) have been developed in nanotechnology, with most of the chip area occupied by memories. Generally, memories in SOCs contain various sizes with poor accessibility. Thus, it is not easy to repair these memories with the conventional external equipment test method. For this reason, memory designers commonly use the redundancy method for replacing rows–columns with spare ones mainly to improve the yield of the memories. In this manuscript, the Deep Q-learning (DQL) with Bit-Swapping-based linear feedback shift register (BSLFSR) for Fault Detection (DQL-BSLFSR-FD) is proposed for Static Random Access Memory (SRAM). The proposed Deep Q-learning-based memory built-in self-test (MBIST) is used to check the memory array unit for faults. The faults are inserted into the memory using the Deep Q-learning fault injection process. The test patterns and faults injection are controlled during testing using different test cases. Subsequently, fault memory is repaired after inserting faults in the memory cell using the Bit-Swapping-based linear feedback shift register (BSLFSR) based Built-in Self-Repair (BISR) model. The BSLFSR model performs redundancy analysis that detects faulty cells, utilizing spare rows and columns instead of defective cells. The design and implementation of the proposed BIST and Built-in Self-Repair methods are developed on FPGA, and Verilog’s simulation is conducted. Therefore, the proposed DQL-BSLFSR-FD model simulation has attained 23.5%, 29.5% lower maximum operating frequency (minimum clock period), and 34.9%, 26.7% lower total power consumption than the existing approaches.

Section: Introductionmentioning

confidence: 99%

Deep Q-Learning with Bit-Swapping-Based Linear Feedback Shift Register fostered Built-In Self-Test and Built-In Self-Repair for SRAM

Alnatheer

2022

Micromachines

Self Cite

“…Memory built-in self-test (MBIST) is a verified and reliable method for testing embedded memory [7][8][9][10], whereby memories are tested for fault and the fault types using sophisticated March algorithms. The MBIST controller usually works on test algorithms for finding defects and their types in embedded memories [11,12]. Testing the embedded memories by the test-pattern generator (TPG), using a scan chain method, is proposed in the research [13,14] to target less power consumption.…”

Section: Introductionmentioning

confidence: 99%

Optimal Method for Test and Repair Memories Using Redundancy Mechanism for SoC

Alnatheer

2021

Micromachines

Self Cite

The current system-on-chip (SoC)-based devices uses embedded memories of enormous size. Most of these systems’ area is dense with memories and promotes different types of faults appearance in memory. The memory faults become a severe issue when they affect the yield of the product. A memory-test and -repair scheme is an attractive solution to tackle this kind of problem. The built-in self-repair (BISR) scheme is a prominent method to handle this issue. The BISR scheme is widely used to repair the defective memories for an SoC-based system. It uses a built-in redundancy analysis (BIRA) circuit to allocate the redundancy when defects appear in the memory. The data are accessed from the redundancy allocation when the faulty memory is operative. Thus, this BIRA scheme affects the area overhead for the BISR circuit when it integrates to the SoC. The spare row and spare column–based BISR method is proposed to receive the optimal repair rate with a low area overhead. It tests the memories for almost all the fault types and repairs the memory by using spare rows and columns. The proposed BISR block’s performance was measured for the optimal repair rate and the area overhead. The area overhead, timing, and repair rate were compared with the other approaches. Furthermore, the study noticed that the repair rate and area overhead would increase by increasing the spare-row/column allocation.

“…This research consists of two methods, first to test the memories and second one to repair the memories for fault. There are existing approaches available to test the memories for failures but can be further enhanced to get better results [7][8][9][10][11]27]. Among the various test techniques of memories, the algorithmic test approach retained its positions for a long time [12].…”

Section: Introductionmentioning

confidence: 99%

“…The algorithmic approach is fast and provides better fault coverage [8]. The stuck-at fault, transition fault, address decoder faults, neighbourhood pattern sensitive faults (NPSF), and coupling faults computes by memory built-in self-test (MBIST) approach [8,11,[20][21][22]. The research approaches [28][29][30] are not able to detect all fault types in semiconductor memories.…”

Section: Introductionmentioning

confidence: 99%

“…They identify only stackat fault, address decoder faults, transition faults, and only some coupling faults. The coupling faults are detected using a March-ee algorithm in the research [11]. Memory repair is a standard method for yield improvement for today's modern SoC design.This process usually consists of memory test, redundancy analysis (RA) and repair mechanism.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Memory test and repair technique for SoC based devices

IEICE Electron. Express

Eljialy

Ahmad

2021

Self Cite

System on Chip (SoC) architecture mainly consists of the memories in a larger area. Due to the availability of memories in a largersize, it is difficult to test these memories for faults. Therefore, a smooth test solution to test these memories against fault and repair the faulty cells has introduced. In this research, we proposed a Memory Test Controller (MTC) to test the memories and Built-in Self-repair (BISR) mechanism to repair the faulty cells for any recent SoC based devices. The MTC not only identifies the fault, but it finds the type of fault available, and BISR block repairs the detected faulty cells. The paper provides empirical insights about how change is brought in features of the SoC based device after integrating both the proposed controller block. It is noticed that from the obtained results, the proposed methods are stands better in terms of the area overhead, power and timing when compared with the existing approaches.